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OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
IDT82V2048
FEATURES
Fully integrated octal T1/E1 short haul line interface which supports 100 T1 twisted pair, 120 E1 twisted pair and 75 E1 coaxial applications Selectable single rail or dual rail mode and AMI or HDB3/B8ZS line encoder/decoder Built-in transmit pre-equalization meets G.703 & T1.102 Selectable transmit/receive jitter attenuator meets ETSI CTR12/ 13, ITU G.736, G.742,G.823 and AT&T Pub 62411 specifications SONET/SDH optimized jitter attenuator meets ITU G.783 mapping jitter specification Digital/analog LOS detector meets ITU G.775, ETS 300 233 and T1.231

ITU G.772 non-intrusive monitoring for in-service testing for any one of channel1 to channel7 Low impedance transmit drivers with tri-state Selectable hardware and parallel/serial host interface Local, remote and inband loopback test functions Hitless Protection Switching (HPS) for 1 to 1 protection without relays JTAG boundary scan for board test 3.3V supply with 5V tolerant I/O Low power consumption Operating Temperature Range: -40C to +85C Available in 144-pin Thin Quad Flat Pack (TQFP_144_DA) and 160-pin Plastic Ball Grid Array (PBGA) packages
FUNCTIONAL BLOCK DIAGRAM
LOS Detector RTIPn RRINGn Analog Loopback TTIPn TRINGn Peak Detector Line Driver Slicer CLK&Data Recovery (DPLL) Digital Loopback Waveform Shaper Transmit All Ones G.772 Monitor Clock Generator
One of Eight Identical Channels LOSn Jitter Attenuator B8ZS/ HDB3/AMI Decoder Remote Loopback Jitter Attenuator B8ZS/ HDB3/AMI Encoder IBLC Generator IBLC Detector AIS Detector TCLKn TDn/TDPn BPVIn/TDNn RCLKn RDn/RDPn CVn/RDNn
Control Interface
Register File
JTAG TAP
VDD IO VDDT VDDD VDDA
OE CLKE MODE[2:0] CS/JAS TS2/SCLK/ALE/AS TS1/RD/R/W TS0/SDI/WR/DS SD0/RDY/ACK INT LP/D/AD[7:0] MC/A[4:0]
MCLK
Figure - 1. Block Diagram
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TRST TCK TMS TDI TDO
INDUSTRIAL TEMPERATURE RANGES
1
(c) 2003 Integrated Device Technology, Inc.
DECEMBER 2003
DSC-6037/11
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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DESCRIPTION:
The IDT82V2048 is a single chip, 8-channel T1/E1 short haul PCM transceiver with a reference clock of 1.544MHz (T1) or 2.048MHz (E1). It contains 8 transmitters and 8 receivers. Both the receivers and transmitters can be programmed to work either in single rail mode or dual rail mode. AMI or HDB3/B8ZS encoder/ decoder is selectable in single rail mode. Pre-encoded transmit data in NRZ format can be accepted when the device is configured in dual rail mode. The receivers perform clock and data recovery by using integrated digital phase-locked loop. As an option, the raw sliced data (no retiming) can be output on the receive data pins. Transmit equalization is implemented with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. A jitter attenuator is integrated in the IDT82V2048 and can be switched into either the transmit path or the receive path for all chan-
nels. The jitter attenuation performance meets ETSI CTR12/13, ITU G.736, G.742, G.823, and AT&T Pub 62411 specifications. The IDT82V2048 offers hardware control mode and software control mode. Software control mode works with either serial host interface or parallel host interface. The latter works via an Intel/Motorola compatible 8-bit parallel interface for both multiplexed or non-multiplexed applications. Hardware control mode uses multiplexed pins to select different operation modes when the host interface is not available to the device. The IDT82V2048 also provides loopback and JTAG boundary scan testing functions. Using the integrated monitoring function, the IDT82V2048 can be configured as a 7-channel transceiver with non-intrusive protected monitoring points. The IDT82V2048 can be used for SDH/SONET multiplexers, central office or PBX, digital access cross connects, digital radio base stations, remote wireless modules and microwave transmission systems.
PIN CONFIGURATIONS
TD4/TDP4 TCLK4 LOS5 CV5/RDN5 RD5/RDP5 RCLK5 BPVI5/TDN5 TD5/TDP5 TCLK5 TDI TDO TCK TMS TRST IC IC VDDIO GNDIO VDDA GNDA MODE0/CODE CS/JAS TS2/SCLK/ALE/AS TS1/RD/R/W TS0/SDI/WR/DS SDO/RDY/ACK INT TCLK2 TD2/TDP2 BPVI2/TDN2 RCLK2 RD2/RDP2 CV2/RDN2 LOS2 TCLK3 TD3/TDP3 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TD7/TDP7 TCLK7 LOS6 CV6/RDN6 RD6/RDP6 RCLK6 BPVI6/TDN6 TD6/TDP6 TCLK6 MCLK MODE2 A4 MC3/A3 MC2/A2 MC1/A1 MC0/A0 VDDIO GNDIO VDDD GNDD LP0/D0/AD0 LP1/D1/AD1 LP2/D2/AD2 LP3/D3/AD3 LP4/D4/AD4 LP5/D5/AD5 LP6/D6/AD6 LP7/D7/AD7 TCLK1 TD1/TDP1 BPVI1/TDN1 RCLK1 RD1/RDP1 CV1/RDN1 LOS1 TCLK0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
BPVI4/TDN4 RCLK4 RD4/RDP4 CV4/RDN4 LOS4 OE CLKE VDDT4 TTIP4 TRING4 GNDT4 RTIP4 RRING4 GNDT5 TRING5 TTIP5 VDDT5 RRING5 RTIP5 VDDT6 TTIP6 TRING6 GNDT6 RTIP6 RRING6 GNDT7 TRING7 TTIP7 VDDT7 RRING7 RTIP7 LOS7 CV7/RDN7 RD7/RDP7 RCLK7 BPVI7/TDN7
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
IDT 82V2048DA
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
BPVI3/TDN3 RCLK3 RD3/RDP3 CV3/RDN3 LOS3 RTIP3 RRING3 VDDT3 TTIP3 TRING3 GNDT3 RRING2 RTIP2 GNDT2 TRING2 TTIP2 VDDT2 RTIP1 RRING1 VDDT1 TTIP1 TRING1 GNDT1 RRING0 RTIP0 GNDT0 TRING0 TTIP0 VDDT0 MODE1 LOS0 CV0/RDN0 RD0/RDP0 RCLK0 BPVI0/TDN0 TD0/TDP0
Figure - 2a. TQFP Package Pin Assignment
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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PIN CONFIGURATIONS (CONTINUED)
A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RCLK 7 RDP 7 RDN 7 VDDT 7 TRING 7
B TCLK 7 TDP 7 TDN 7 VDDT 7 TTIP 7
C RCLK 6 RDP 6 RDN 6 VDDT 6 TRING 6
D TCLK 6 TDP 6 TDN 6 VDDT 6 TTIP 6
E MCLK MODE 2 LOS 6 LOS 7
F MC 1 MC 2 MC 3 A4
G
H
J LP 6 LP 5 LP 4 LP 3
K LP 7 MODE 1 LOS 1 LOS 0
L TCLK 1 TDP 1 TDN 1
M RCLK 1 RDP 1 RDN 1
N TCLK 0 TDP 0 TDN 0
P RCLK 0 RDP 0 RDN 0 VDDT 0 TRING 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
VDDIO VDDD LP 0 MC 0 LP 2 LP 1
GNDIO GNDD
VDDT VDDT VDDT 1 1 0 TTIP 1 TRING 1 TTIP 0
GNDT GNDT GNDT GNDT 7 7 6 6 RTIP RRING 7 7 RTIP RRING 4 4 RTIP 6 RTIP 5 RRING 6 RRING 5
GNDT GNDT GNDT GNDT 1 1 0 0
IDT 82V2048BB (Bottom View)
RRING RTIP 1 1 RRING RTIP 2 2
RRING 0 RRING 3
RTIP 0 RTIP 3
GNDT GNDT GNDT GNDT 4 4 5 5 TRING 4 VDDT 4 RDN 4 RDP 4 RCLK 4 A TTIP 4 VDDT 4 TDN 4 TDP 4 TCLK 4 B TRING 5 VDDT 5 RDN 5 RDP 5 RCLK 5 C TTIP 5 VDDT 5 TDN 5 TDP 5 TCLK 5 D LOS 4 LOS 5 CLKE OE E TMS TDI TDO TCK F GNDIO GNDA TRST IC MODE 0 IC CS TS 2 TS 1 TS 0 J LOS 3 LOS 2 INT SDO K
GNDT GNDT GNDT GNDT 2 2 3 3 TTIP 2 TRING 2 TTIP 3 TRING 3 VDDT 3 RDN 3 RDP 3 RCLK 3 P
VDDT VDDT VDDT 2 2 3 TDN 2 TDP 2 TCLK 2 L RDN 2 RDP 2 RCLK 2 M TDN 3 TDP 3 TCLK 3 N
VDDIO VDDA G H
Figure - 2b. PBGA160 Package Pin Assignment
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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PIN DESCRIPTION
Name TTIP0 TTIP1 TTIP2 TTIP3 TTIP4 TTIP5 TTIP6 TTIP7 TRING0 TRING1 TRING2 TRING3 TRING4 TRING5 TRING6 TRING7 RTIP0 RTIP1 RTIP2 RTIP3 RTIP4 RTIP5 RTIP6 RTIP7 RRING0 RRING1 RRING2 RRING3 RRING4 RRING5 RRING6 RRING7
1
Type
Pin No. QFP144 BGA160 45 52 57 64 117 124 129 136 46 51 58 63 118 123 130 135 48 55 60 67 120 127 132 139 49 54 61 66 121 126 133 138 N5 L5 L10 N10 B10 D10 D5 B5 P5 M5 M10 P10 A10 C10 C5 A5 P7 M7 M8 P8 A8 C8 C7 A7 N7 L7 L8 N8 B8 D8 D7 B7
Description Transmit and Receive Line Interface TTIPn/TRINGn: Transmit Bipolar Tip/Ring for Channel 0~7 These pins are the differential line driver outputs. They will be in high impedance state if pin OE is low or the corresponding pin TCLKn is low (pin OE is globe control, while pin TCLKn is perchannel control). In host mode, each pin can be in high impedance state by programming a "1" to the corresponding bit in Register OE1.
Analog Output
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 0~7 These pins are the differential line receiver inputs.
Analog Input
Register name is indicated by bold capital letter. OE: Output Enable Register.
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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PIN DESCRIPTION (CONTINUED)
Name TD0/TDP0 TD1/TDP1 TD2/TDP2 TD3/TDP3 TD4/TDP4 TD5/TDP5 TD6/TDP6 TD7/TDP7 I BPVI0/TDN0 BPVI1/TDN1 BPVI2/TDN2 BPVI3/TDN3 BPVI4/TDN4 BPVI5/TDN5 BPVI6/TDN6 BPVI7/TDN7 38 31 79 72 109 102 7 144 N3 L3 L12 N12 B12 D12 D3 B3 Type Pin No. QFP144 BGA160 N2 37 L2 30 L13 80 N13 73 B13 108 D13 101 D2 8 B2 1 Description TDn: Transmit Data for Channel 0~7 When the device is in Single Rail Mode, the NRZ data to be transmitted is input on this pin. Data on TDn is sampled into the device on falling edges of TCLKn, and encoded by AMI or HDB3/B8ZS line code rules before being transmitted to the line. BPVIn: Bipolar Violation Insertion for Channel 0~7 Bipolar violation insertion is available in Single Rail Mode 2 (see table-1) with AMI enabled. A low-tohigh transition on this pin will make the next logic one to be transmitted on TDn the same polarity as the previous pulse, and violate the AMI rule. This is for testing. TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7 When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input on this pin. Data on TDPn/TDNn are active high and sampled on falling edge of TCLKn. The line code in dual rail mode is as the follows : TDPn TDNn Output Pulse 0 0 Space 0 1 Negative Pulse 1 0 Positive Pulse 1 1 Space Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding channel into single rail mode 1 (see table-1 on Page14). TCLKn: Transmit Clock for Channel 0~7 The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The transmit data at TDn/TDPn or TDNn is sampled into the device on falling edge of TCLKn. Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All One (TAO) state (when MCLK is clocked). In TAO state, the TAO generator adopts MCLK as the time reference. If TCLKn is Low, the corresponding transmit channel is set into power down state, while driver output ports become high impedance. Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the follows: MCLK TCLKn Transmitter Mode Clocked Clocked Normal operation Clocked High ( 16 MCLK) Transmit All One (TAO) signals to the line side in the corresponding transmit channel. Clocked Low ( 64 MCLK) Corresponding transmit channel is set into power down state. High/Low TCLK1 is clocked TCLKn is clocked Normal operation TCLKn is high Transmit All One (TAO) signals to the line side in the corresponding transmit channel. ( 16 TCLK1) TCLKn is low Corresponding transmit channel is set into power down state. ( 64 TCLK1) The receive path is not affected by the status of TCLK1. When MCLK is high, all receive paths just slice the incoming data stream. When MCLK is low, all the receive paths are powered down. High/Low TCLK1 is not All eight transmitters (TTIPn & TRINGn) will be in high impedance available state. (High/Low)
TCLK0 TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7
I
36 29 81 74 107 100 9 2
N1 L1 L14 N14 B14 D14 D1 B1
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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PIN DESCRIPTION (CONTINUED)
Pin No. QFP144 BGA160 P2 RD0/RDP0 O 40 M2 RD1/RDP1 33 M13 RD2/RDP2 Tri-state 77 P13 RD3/RDP3 70 A13 111 RD4/RDP4 C13 104 RD5/RDP5 C2 5 RD6/RDP6 A2 142 RD7/RDP7 Name Type CV0/RDN0 CV1/RDN1 CV2/RDN2 CV3/RDN3 CV4/RDN4 CV5/RDN5 CV6/RDN6 CV7/RDN7 41 34 76 69 112 105 4 141 P3 M3 M12 P12 A12 C12 C3 A3 Description RDn: Receive Data for Channel 0~7 In Single Rail Mode, the received NRZ data is output on this pin. The data is decoded by AMI or HDB3/B8ZS line code rule. CVn: Code Violation for Channel 0~7 In Single Rail Mode, the bipolar violation, code violation and excessive zeros will be reported by driving pin CVn to high level for a full clock cycle. However, only bipolar violation is indicated when AMI decoder is selected. RDPn/RDNn: Positive/Negative Receive Data for Channel 0~7 In Dual Rail Mode with clock recovery, these pins output the NRZ data. A high signal on RDPn indicates the receipt of a positive pulse on RTIPn/RRINGn while a high signal on RDNn indicates the receipt of a negative pulse on RTIPn/RRINGn. The output data at RDn or RDPn/RDNn are valid on the falling edges of RCLK when the CLKE input is in High level, or valid on the rising edges of RCLK when CLKE is Low. In Dual Rail Mode without clock recovery, these pins output he raw RZ sliced data. In this data t recovery mode, the active polarity of RDPn/RDNn is determined by pin CLKE. When pin CLKE is Low, RDPn/RDNn is active low. When pin CLKE is High, RDPn/RDNn is active high. In hardware mode, RDn or RDPn/RDNn will remain active during LOS. In host mode, these pins will either remain active or insert alarm indication signal (AIS) into the receive path, determined by bit AISE in register GCF (Global Configuration register). RDn or RDPn/RDNn is set into high impedance when the corresponding receiver is power down. RCLKn: Receive Clock for Channel 0~7 In clock recovery mode, this pin outputs the recovered clock from signal received on RTIPn/RRINGn. The received data are clocked out of the device on rising edges of RCLKn if pin CLKE is low, or on falling edges of RCLKn if pin CLKE is high. In data recovery mode, RCLKn is the output of an internal exclusive OR (XOR) which is connected with RDPn and RDNn. The clock is recovered from the signal on RCLKn externally. If receiver n is power down, the corresponding RCLKn is in high impedance. MCLK: Master Clock This is the independent, free running reference clock. A clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) is supplied to this pin as the clock reference of the device for normal operation. In receive path, when MCLK is high, the device slices the incoming bipolar line signal into RZ pulse (Data Recovery mode). When MCLK is low, all the receivers are power down, and the output pins RCLKn, RDPn and RDNn are switched to high impedance. In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (see TCLKn pin description for detail). Note that wait state generation via RDY/ACK is not available if MCLK is not provided. LOSn: Loss of Signal Output for Channel 0~7 A high level on this pin indicates the loss of signal when there is no transition over a specified period of time and no enough ones density in the received signal. The transition will return to low automatically when there is enough transitions over a specified period of time with a certain ones density in the received signal. The LOS assertion and desertion criteria are described in the Functional Description.
RCLK0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 MCLK
O Tri-state
I
39 32 78 71 110 103 6 143 10
P1 M1 M14 P14 A14 C14 C1 A1 E1
LOS0 LOS1 LOS2 LOS3 LOS4 LOS5 LOS6 LOS7
O
42 35 75 68 113 106 3 140
K4 K3 K12 K11 E11 E12 E3 E4
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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PIN DESCRIPTION (CONTINUED)
Name MODE2 Type I (Pulled to VDDIO / 2) Pin No. QFP144 BGA160 11 E2 Description Hardware/Host Control Mode MODE2: Control Mode Select 2 The signal on this pin determines which control mode is selected to control the device: MODE2 Control Interface Low Control by Hardware mode VDDIO/2 Control by Serial Host Interface High Control by Parallel Host Interface Hardware control pins include MODE[2:0], TS[2:0], LOOP[7:0], CODE, CLKE, JAS and OE. Serial host Interface pins include CS, SCLK, SDI, SDO and INT . Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions below for details): MODE[2:0] Host Interface 100 Non-multiplexed Motorola mode interface. 101 Non-multiplexed Intel mode interface. 110 Multiplexed Motorola mode interface. 111 Multiplexed Intel mode interface. MODE1: Control Mode Select 1 In parallel host mode, the parallel interface operates with separate address bus and data bus when this pin is Low, and operates with multiplexed address and data bus when this pin is High. In serial host mode or hardware mode, this pin should be grounded. MODE0: Control Mode Select 0 In host mode, the parallel host interface is configured for Motorola compatible hosts when this pin is Low, or for Intel compatible hosts when this pin is High. CODE: Line Code Rule Select In hardware control mode, the B8ZS (for T1 mode)/ HDB3 (for E1 mode) encoder/decoder is enabled when this pin is Low, and AMI encoder/decoder is enabled when this pin is High. The selections affect all the channels. CS/JAS I (Pulled to VDDIO / 2) 87 J11 In serial host mode, this pin should be grounded. CS: Chip Select (Active Low) In host mode, this pin is asserted low by the host to enable host interface. A transition from High to Low must occur on this pin for each Read/Write operation and the level must not return to High until the operation is over. JAS: Jitter Attenuator Select In hardware control mode, this pin globally determines the Jitter Attenuator position: JAS Jitter Attenuator (JA) Configuration Low JA in transmit path VDDIO/2 JA not used High JA in receive path
MODE1
I
43
K2
MODE0 /CODE
I
88
H12
7
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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PIN DESCRIPTION (CONTINUED)
Name Type TS2/ SCLK/ ALE/AS I Pin No. Description QFP144 BGA160 86 J12 TS2: Template Select 2 In hardware control mode, the signal on this pin is the most significant bit for the transmit template select. Refer to Transmit Template of the Functional Description for details. SCLK: Shift Clock In serial host mode, the signal on this pin is the shift clock for the serial interface. Data on pin SDO is clocked out on falling edges of SCLK if pin CLKE is Low, or on rising edges of SCLK if pin CLKE is High. Data on pin SDI is always sampled on rising edges of SCLK. ALE: Address Latch Enable In parallel Intel multiplexed host mode, the address on AD[4:0] is sampled into the device on falling edges of ALE (signals on AD[7:5] are ignored). In non-multiplexed host mode, ALE should be pulled High. AS: Address Strobe (Active Low) In parallel Motorola multiplexed host mode, the address on AD[4:0] is latched into the device on falling edges of AS (signals on AD[7:5] are ignored). In non-multiplexed host mode, AS should be pulled High. TS1: Template Select 1 In hardware control mode, the signal on this pin is the second most significant bit for the transmit template select. Refer to Transmit Template of Functional Description for details. RD: Read Strobe (Active Low) In parallel Intel multiplexed or non-multiplexed host mode, this pin is active low for read operation. R/W: Read/Write Select In parallel Motorola multiplexed or non-multiplexed host mode, the pin is active low for write operation and high for read operation. TS0: Template Select 0 In hardware control mode, the signal on this pin is the least significant bit for the transmit template select. Refer to Transmit Template of Functional Description for details. SDI: Serial Data Input In serial host mode, this pin input the data to the serial interface. Data on this pin is sampled on rising edges of SCLK. WR: Write Strobe (Active Low) In parallel Intel host mode, this pin is active low during write operation. The data on D[7:0] (in nonmultiplexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on rising edges of WR. DS: Data Strobe (Active Low) In parallel Motorola host mode, this pin is active low. During a write operation (R/W = 0), the data on D[7:0] (in non-multiplexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on rising edges of DS. During a read operation (R/W = 1), the data is driven to D[7:0] (in non-multiplexed mode) or AD[7:0] (in multiplexed mode) by the device on rising edges of DS. In parallel Motorola non-multiplexed host mode, the address information on the 5 bits of address bus A[4:0] are latched into the device on the falling edge of DS.
TS1/RD /R/W
I
85
J13
TS0/ SDI/WR /DS
I
84
J14
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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PIN DESCRIPTION (CONTINUED)
Name SDO /RDY /ACK Type O Pin No. Description QFP144 BGA160 83 K14 SDO: Serial Data Output In serial host mode, the data is output on this pin. In serial write operation, SDO is always in High impedance. In serial read operation, SDO is in High impedance only when SDI is in address/command byte. Data on pin SDO is clocked out of the device on falling edges of SCLK if pin CLKE is Low, or on rising edges of SCLK if pin CLKE is High. RDY: Ready Output In parallel Intel host mode, the high level of this pin reports to the host that bus cycle can be completed, while low reports the host must insert wait states. ACK : Acknowledge Output (Active Low) In parallel Motorola host mode, the low level of this pin indicates that valid information on the data bus is ready for a read operation or acknowledges the acceptance of the written data during a write operation. INT : Interrupt (Active Low) This is the open drain, active low interrupt output. Four sources may cause the interrupt (refer to Interrupt Handling of Functional Description for details). LPn: Loopback Select 7~0 In hardware control mode, pin LPn configures the corresponding channel in different loopback mode, as follows: LPn Loopback Configuration Low Remote loopback. VDDIO/2 No loopback. High Analog loopback. Refer to Loopback Configuration of Functional Description for details. Dn: Data Bus 7~0 In non-multiplexed host mode, these pins are the bi-directional data bus. ADn: Address/Data Bus 7~0 In multiplexed host mode, these pins are the multiplexed bi-directional address/data bus. In serial host mode, these pins should be grounded.
INT
LP7/D7/AD7 LP6/D6/AD6 LP5/D5/AD5 LP4/D4/AD4 Tri-state LP3/D3/AD3 LP2/D2/AD2 LP1/D1/AD1 LP0/D0/AD0
O Open Drain I/O
82 28 27 26 25 24 23 22 21
K13 K1 J1 J2 J3 J4 H2 H3 G2
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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PIN DESCRIPTION (CONTINUED)
Name A4 MC3/A3 MC2/A2 MC1/A1 MC0/A0 Type I Pin No. QFP144 BGA160 F4 12 F3 13 F2 14 F1 15 G3 16 Description MCn: Performance Monitor Configuration 4~0 In hardware control mode, A4 must be connected to GND. MC[3:0] are used to select one transmitter or receiver of the channel 1 to 7 for non-intrusive monitoring. Channel 0 is used as the monitoring channel. If a transmitter is monitored, signals on the corresponding pins TTIPn and TRINGn are internally transmitted to RTIP0 and RRING0. If a receiver is monitored, signals on the corresponding pins RTIPn and RRINGn are internally transmitted to RTIP0 and RRING0. The clock and data recovery circuit in receiver 0 can then output the monitored clock to pin RCLK0 as well as the monitored data to RDP0 and RDN0 pins. The signals monitored by channel 0 can be routed to TTIP0/TRING0 by activating the remote loopback in this channel. Performance Monitor Configuration determined by MC[3:0] is shown below. Note that if MC[2:0] = 000, the device is in normal operation of all the channels. MC[3:0] Monitoring Configuration 0000 Normal operation without monitoring. 0001 Monitoring receiver 1. 0010 Monitoring receiver 2. 0011 Monitoring receiver 3. 0100 Monitoring receiver 4. 0101 Monitoring receiver 5. 0110 Monitoring receiver 6. 0111 Monitoring receiver 7. 1000 Normal operation without monitoring. 1001 Monitoring transmitter 1. 1010 Monitoring transmitter 2. 1011 Monitoring transmitter 3. 1100 Monitoring transmitter 4. 1101 Monitoring transmitter 5. 1110 Monitoring transmitter 6. 1111 Monitoring transmitter 7. An: Address Bus 4~0 When pin MODE1 is low, the parallel host interface operates with separate address and data bus. In this mode, the signal on this pin is the address bus of the host interface. OE: Output Driver Enable Pulling this pin to low can make all driver output into high impedance state immediately for redundancy application without external mechanical relays. In this condition, all the other internal circuits remain active. CLKE: Clock Edge Select The signal on this pin determines the active edge of RCLKn and SCLK in clock recovery mode, or determines the active level of RDPn and RDNn in the data recovery mode. (Refer to Functional Description and Table-2).
OE
I
114
E14
CLKE
I
115
E13
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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PIN DESCRIPTION (CONTINUED)
Name TRST TMS TCK Type I Pullup I Pullup I Pin No. QFP144 BGA160 95 96 97 G12 F11 F14 Description JTAG Signals TRST: JTAG Test Port Reset (Active Low) This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pullup resistor and it can be left disconnected. TMS: JTAG Test Mode Select The signal on this pin controls the JTAG test performance and is clocked into the device on rising edges of TCK. This pin has an internal pullup resistor and it can be left disconnected. TCK: JTAG Test Clock This pin input the clock of the JTAG Test. The data on TDI and TMS are clocked into the device on rising edges of TCK, while the data on TDO is clocked out of the device on falling edges of TCK. TDO: JTAG Test Data Output This pin output the serial data of the JTAG Test. The data on TDO is clocked out of the device on falling edges of TCK. TDO is a Tri-state output signal. It is active only when scanning of data is out. TDI: JTAG Test Data Input This pin input the serial data of the JTAG Test. The data on TDI is clocked into the device on rising edges of TCK. This pin has an internal pullup resistor and it can be left disconnected. IC: Internal Connected (Leave it open for normal operation.) IC: Internal Connected (Leave it open for normal operation.) Supplies and Grounds 3.3V I/O Power Supply I/O GND 3.3V / 5V Power Supply for Transmitter Driver All VDDT pins must be connected to either 3.3V or 5V. It is not allowed to leave any of the VDDT pins open (not-connected) even if the channel is not used.
TDO
O Tri-state
98
F13
TDI
I Pull up
99
F12
IC IC VDDIO GNDIO VDDT0 VDDT1 VDDT2 VDDT3 VDDT4 VDDT5 VDDT6 VDDT7 GNDT0 GNDT1 GNDT2 GNDT3 GNDT4 GNDT5 GNDT6 GNDT7 VDDD VDDA GNDD GNDA
-
93 94 17 92 18 91 44 53 56 65 116 125 128 137 47 50 59 62 119 122 131 134 19 90 20 89
G13 H13 G1 G14 G4 G11 N4,P4 L4,M4 L11,M11 N11,P11 A11,B11 C11,D11 C4,D4 A4,B4 N6,P6 L6,M6 L9,M9 N9,P9 A9,B9 C9,D9 C6,D6 A6,B6 H1 H14 H4 H11
-
Analog GND for Transmitter Driver
-
3.3V Digital / Analog Core Power Supply Digital / Analog Core GND
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
OVERVIEW The IDT82V2048 is a fully integrated octal short-haul line interface unit, which contains eight transmit and receive channels for use in either E1 or T1 applications. The receiver performs clock and data recovery. As an option, the raw sliced data (no retiming) can be output to the system. Transmit equalization is implemented with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. A selectable jitter attenuation may be placed in the receive path or the transmit path. Moreover, multiple testing functions, such as error detection, loopback and JTAG boundary scan are also provided. The device is optimized for flexible software control through a serial or parallel host mode interface. Hardware control is also available. Figure-1 shows One of the Eight Identical Channels operation. T1 / E1 MODE SELECTION T1/E1 mode selection configures the device globally. In Hardware Mode, the template selection pins: TS2, TS1 and TS0 determine whether the operation mode is T1 or E1 (refer to Table-7). In Software Mode, the Transmit Template Select Register (Primary Register: 11Hex) determines whether the operation mode is T1 or E1. SYSTEM INTERFACE The system interface of each channel can be configured to operate in different modes: 1. Single Rail interface with clock recovery. 2. Dual Rail interface with clock recovery. 3. Dual Rail interface with data recovery (that is, with raw data slicing only and without clock recovery).
Therefore, each signal pin on system side has multiple functions depending on which operation mode the device is in. The Dual Rail interface consists of TDPn 1, TDNn, TCLKn, RDPn, RDNn and RCLKn. Data transmitted from TDPn and TDNn appears on TTIPn and TRINGn at the line interface; data received from the RTIPn and RRINGn at the line interface are transferred to RDPn and RDNn while the recovered clock extracting from the received data stream outputs on RCLKn. In Dual Rail operation, the clock/data recovery mode is selectable. Dual Rail interface with clock recovery shown in Figure-3 is a default configuration mode. Dual Rail interface with data recovery is shown in Figure-4. Pin RDPn and RDNn, in this condition, are raw RZ slice output and internally connected to an EXOR which is fed to the RCLKn output for external clock recovery applications. In Single Rail Mode, data transmitted from TDn appears on TTIPn and TRINGn at the line interface. Data received from the RTIPn and RRINGn at the line interface appears on RDn while the recovered clock extracting from the received data stream outputs on RCLKn. When the device is in single rail interface, the selectable AMI or HDB3/B8ZS line encoder/decoder is available and any code violation in the received data will be indicated at the CVn pin. The Single Rail Mode can be devided into 2 sub-modes. Single Rail Mode 1, whose interface is composed of TDn, TCLKn, RDn, CVn and RCLKn, is realized by pulling pin TDNn to high for more than 16 consecutive TCLK cycles. Single Rail Mode 2, whose interface is composed of TDn, TCLKn, RDn, CVn, RCLKn and BPVIn, is realized by setting bit CRS in e-CRS2 and bit SING in e-SING. The difference between them is that, in the latter mode bipolar violation can be inserted via pin BPVIn if AMI line code is selected. The configuration of different system interface is summarized in Table-1.
LOS Detector RTIPn RRINGn Peak Detector TTIPn TRINGn Line Driver Waveform Shaper Transmit All Ones Slicer CLK&Data Recovery (DPLL)
One of Eight Identical Channels LOSn Jitter Attenuator B8ZS/ HDB3/AMI Decoder RCLKn RDPn RDNn
Jitter Attenuator
B8ZS/ HDB3/AMI Encoder
TCLKn TDPn TDNn
Figure - 3. Dual Rail Interface with Clock Recovery 3
NOTE: 1. The footprint `n' (n = 0 - 7) indicates one of the eight channels 2. The first letter "e-"indicates expanded register. 3. The grey blocks are bypassed and the dotted blocks are selectable
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
LOS Detector RTIPn RRINGn Peak Detector TTIPn TRINGn Line Driver Waveform Shaper Transmit All Ones Slicer CLK&Data Recovery (DPLL)
One of Eight Identical Channels LOSn Jitter Attenuator B8ZS/ HDB3/AMI Decoder RCLKn (RDP RDN) RDPn RDNn
Jitter Attenuator
B8ZS/ HDB3/AMI Encoder
TCLKn TDPn TDNn
Figure - 4. Dual Rail Interface with Data Recovery
LOS Detector RTIPn RRINGn Peak Detector TTIPn TRINGn Line Driver Waveform Shaper Transmit All Ones Slicer CLK&Data Recovery (DPLL)
One of Eight Identical Channels LOSn Jitter Attenuator HDB3/ B8ZS/AMI Decoder RCLKn RDn CVn
Jitter Attenuator
HDB3/ B8ZS/AMI Encoder
TCLKn TDn TDNn/BPVIn
Figure - 6. Single Rail Mode
13
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 1a. SYSTEM INTERFACE CONFIGURATION (Hardware Mode) Hardware Mode MCLK clocked clocked H L TDNn H ( 16 MCLK) pulse pulse pulse Interface Single Rail mode 1 Dual Rail with Clock Recovery Receive just slice the incoming data. Transmit is determined by the status of TCLKn. Receive is power down. Transmit is determined by the status of TCLKn.
TABLE - 1b. SYSTEM INTERFACE CONFIGURATION (Host Mode) Host Mode SINGn in e-SING 0 1 0 0 -
MCLK clocked clocked clocked clocked H L
TDNn H pulse pulse pulse pulse pulse
CRSn in e-CRS 0 0 0 1 -
Interface Single Rail mode 1 Single Rail mode 2 Dual Rail with Clock Recovery Dual Rail with Data Recovery Receive just slice the incoming data. Transmit is determined by the status of TCLKn. Receive is power down. Transmit is determined by the status of TCLKn.
TABLE - 2. ACTIVE CLOCK EDGE AND ACTIVE LEVEL
Pin CLKE Low High RD/RDP and CV/RDN Clock recovery Slicer output RCLK Active High Active High Active Low Active High SDO SCLK Active High Active High
RCLK
SCLK
CLOCK EDGES The active edge of RCLK and SCLK(serial interface clock) are also selectable. If pin CLKE is Low, the active edge of RCLK is the rising edge, as for SCLK, that is falling edge. On the contrary, if CLKE is High, the active edge of RCLK is the falling edge and that of SCLK is rising edge. Pins RDn/RDPn, CVn/RDNn and SDO are always active high, and those output signals are valid on the active edge of RCLK and SCLK respectively. See Table-2 for details. However, in dual rail mode without clock recovery, pin CLKE is used to set the active level for RDPn/RDNn raw slicing output: High for active high polarity and Low for active low. It should be noted that data on pin SDI are always active high and is sampled on the rising edge of SCLK. The data on pin TD/TDP or BPVI/ TDN are also always active high but is sampled on the falling edge of TCLK, despite the level on CLKE.
RECEIVER In receive path, the line signals couple into RRINGn and RTIPn via a transformer and are converted into RZ digital pulses by a data slicer. Adaptation for attenuation is achieved using an integral peak detector that sets the slicing levels. Clock and data are recovered from the received RZ digital pulses by a digital phase-locked loop that provides excellent jitter accommodation. After passing through the selectable jitter attenuator, the recovered data are decoded using B8ZS/HDB3 or AMI line code rules and clocked out of pin RDn in single rail mode, or presented on RDPn/RDNn in an undecoded dual rail NRZ format. Loss of signal, alarm indication signal, line code violations and excessive zero are detected. The presence of programmable inband loopback codes are also detected. These various changes in status may be enabled to generate interrupts. Peak Detector and Slicer The slicer determines the presence and polarity of the received pulses. In data recovery mode, the raw positive slicer output appears on
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
RDPn while the negative slicer output appears on RDNn. In clock and data recovery mode, the slicer output is sent to Clock and Data Recovery circuit for abstracting retimed data and optional decoding. The slicer circuit has a built-in peak detector from which the slicing threshold is derived. The slicing threshold is default to 50% (typical) of the peak value. Signals with an attenuation of up to 12 dB (from 2.4V) can be recovered accurately by the receiver. To provide immunity from impulsive noise, the peak detectors are held above a minimum level of 0.150 V typically, despite the received signal level. Clock and Data Recovery The function of Clock and Data Recovery is accomplished by Digital Phase Locked Loop (DPLL). The DPLL is clocked 16 times of the received clock rate, i.e. 24.704 MHz in T1 mode or 32.768 MHz in E1 mode. The recovered data and clock from DPLL is then sent to the selectable Jitter Attenuator or decoder circuit for further processing. The clock recovery and data recovery mode can be selected on per channel basis by setting the bit CRSn in e-CRS. When bit CRSn is defaulted to `0', the corresponding channel operates in data and clock recovery mode. The recovered clock is output on pin RCLKn and retimed NRZ data are output on pin RDPn/RDNn in dual rail mode or on RDn in single rail mode. When CRSn is `1', dual rail with data recovery mode is enabled in the corresponding channel and the clock recovery function is bypassed. In this condition, the analog line signal are converted to RZ digital bit streams on the RDPn/RDNn pins and internally connected to an EXOR which is fed to the RCLKn output for external clock recovery applications. Moreover, Pulling MCLK to H level, all the receivers will enter the dual rail with data recovery mode. In this case, e-CRS is ignored.
B8ZS/HDB3/AMI Line Code Rule Selectable B8ZS/HDB3 or AMI line coding/decoding is provided when the device is configured in single rail mode. B8ZS rules for T1 or HDB3 rules for E1 is enabled by setting bit CODE in register GCF (global control configuration) to `0' or pulling pin CODE to Low. AMI rule is enabled by setting bit CODE in GCF to `1' or pulling pin CODE to High. All the setting above are effected to eight channels. Individual line code rule selection for each channel, if need, is available by setting bit SINGn in e-SING to `1' (to activate bit CODEn in eCODE) and programming bit CODEn to select line code rules in the corresponding channel: `0' for B8ZS/HDB3, while `1' for AMI. In this case, the value in bit CODE in GCF or pin CODE for global control is unaffected in the corresponding channel and only affect in other channels. In dual rail mode, the decoder/encoder are bypassed. Bit CODE in GCF, bit CODEn in e-CODE and pin CODE are ignored. The configuration of the Line Code Rule is summarized in Table-3. Loss of Signal (LOS) Detection The Loss of Signal Detector monitors the amplitude and density of the received signal on Receiver line before the transformer (measured on port A, B in Figure 12). The loss condition is reported by pulling pin LOSn to high. In the same time, LOS alarm registers track LOS condition. When LOS detected or cleared, an interrupt will generate if not masked. In host mode, the detection supports the ANSI T1.231 for T1 mode and ITU-G.775 and ETSI 300233 for E1 mode. In hardware mode, it only supports the ITU-G.775 and ANSI T1.231 specification. Table-4 summarizes the conditions of LOS in clock recovery mode. In data recovery mode, the LOS condition is cleared upon detecting the signal level exceeds 540mV. During LOS, the RDPn/RDNn output the sliced data when bit AISE in
TABLE - 3. CONFIGURATION OF THE LINE CODE RULE Hardware Mode CODE L H Line Code Rule All channels in HDB3/B8ZS All channels in AMI Host Mode CODE in GCF CODEn in e-CODE SINGn in e-SINGn 0 0/1 0 0 0 1 1 0/1 0 1 1 1 0 1 1 1 0 1
Line Code Rule All channels in HDB3/B8ZS All channels in AMI CHn in AMI CHn in HDB3/B8ZS
TABLE - 4. LOS CONDITION IN CLOCK RECOVERY MODE STANDARD G.775 for E1 32 below typ. 310mV (Vpp) 12.5% (4 marks in a sliding 32-bit period) with no more than 15 continuous zeros exceed typ.540mV (Vpp)
15
ANSI T1.231 for T1 LOS Detected LOS Cleared Amplitude Continuous Intervals Amplitude Density 175 below typ. 310mV (Vpp) 12.5% (16 marks in a sliding 128-bit period) with no more than 99 continuous zeros exceed typ. 540mV (Vpp)
ETSI 300233 for E1 2048 (1 ms) below typ. 310mV (Vpp) 12.5% (4 marks in a sliding 32-bit period) with no more than 15 continuous zeros exceed typ. 540mV (Vpp)
Signal on pin LOSn H
L
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
register GCF is 0 or output all ones as AIS (alarm indication signal) when bit AISE is set to 1; The RCLKn is replaced by MCLK only if the AISE is set. Alarm Indication Signal Detection (AIS) Alarm Indication Signal is available only in host mode with clock recovery, as Table-5 shows. Error Detection The device can detects excessive zero, bipolar violations and B8ZS/ HDB3 code violations, refer to figure-7, 8, 9. All the three kinds of errors TABLE - 5. AIS CONDITION ITU G.775 for E1 (register LAC defaulted to 0) AIS detected AIS cleared Less than 3 zeros contained in each of two consecutive 512-bit stream are received 3 or more zeros contained in each of two consecutive 512-bit stream are received
are reported in both host mode and hardware mode with HDB3/B8ZS line code rule is used. Moreover, in host mode, the expanded registers e-CZER and e-CODV are used to determine whether the excessive zero and code violation are reported respectively. When configured in AMI decoding mode, only bipolar violation can be reported. The error detection is available only in single rail mode where the pin RDNn/CVn is used as error report output (CVn pin). The configuration and report status of error detection are summarized in Table-6.
ETSI 300233 for E1 (register LAC is 1) Less than 3 zeros contained in a 512-bit stream are received 3 or more zeros contained in a 512-bit stream are received
ANSI T1.231 for T1 Less than 9 zeros contained in a 8192-bit stream (a ones density of 99.9% over a period of 5.3ms) are received 9 or more zeros contained in a 8192-bit stream are received
TABLE - 6. ERROR DETECTION Hardware Mode Line Code Pin CVn Reports AMI Bipolar Violation HDB3 /B8ZS Bipolar Violation + Code Violation + Excessive Zero Host Mode CODVn in e-CODV CZERn in e-CZER Pin CVn Reports Bipolar Violation 0 0 Bipolar Violation + Code Violation 0 1 Bipolar Violation + Code Violation + Excessive Zero 1 0 Bipolar Violation 1 1 Bipolar Violation + Excessive Zero
Line Code AMI HDB3 /B8ZS
CLK RTIP RRING RD CV Bipolar violation Bipolar Violation detected
1 2
3 4 1 2
5
V 6 3 4 5
7
V
6
Figure - 7. AMI Bipolar Violation
16
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Code violation CLK RTIP RRING RD CV Excessive zero detected Code violation detected
1 4 consecutive zeros 2 1
3 4 2 V 3 4 V
5 6 5 6
Figure - 8. HDB3 Code Violation & Excessive Zero
CLK RTIP RRING RD CV
Excessive zero detected 1 2 3 1 2 3 4 8 consecutive zeros 5 4 5 7 9 6 7 8 6 8
Figure - 9. B8ZS Excessive Zero TRANSMITTER In transmit path, data in NRZ (non return to zero) format are clocked into the device on TDn and encoded by AMI or HDB3/B8ZS line code rules when single rail mode is configured or pre-encoded data in NRZ format are input on TDPn and TDNn when dual rail mode is configured. The data are sampled into the device on falling edges of TCLKn. Jitter attenuator, if enabled, is provided with a FIFO which the data to be transmitted are passing through. A low jitter clock is generated by an integral digital phase-locked loop and is used to read data from the FIFO. The shape of the pulses are user programmable to ensure that the T1/E1 pulse template is met after the signal is passed through different cable lengths or types. Bipolar violation, for diagnosing, can be inserted on pin BPVIn if AMI line code rule is enabled. Waveform Shaper T1 pulse template, specified in the DSX-1 Cross-Connect by ANSI T1.102, is illustrated in Figure-10. The device has built-in transmit waveform templates, corresponding to 5 levels of pre-equalization for cable of a length from 0 to 655ft with each increment of 133ft. E1 pulse template, specified in ITU-T G.703, is shown in Figure-11. The device has built-in transmit waveform templates for cable of 75 or 120. Any one of the six built-in waveform can be chosen in both hardware mode and host mode. Setting the pins TS[2:0] as Table-7 in hardware mode can select the required waveform template for all the transmitters. In host mode, the waveform template can be configured on perchannel basis. Bit TSIA[2:0] in register TSIA is used to select the channel and bit TS[2:0] in register TS is to select the required waveform template. Refer to Register Description for details.
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
The built-in waveform shaper use an internal high frequency clock which is 16XMCLK as clock reference. This function will be bypassed when MCLK is unavailable.
1.2 1 0.8 Normalized Amplitude 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 250 500 Time (ns) 750 1000 1250
Bipolar Violation Insertion When configured in single rail mode 2 with AMI line code enabled, pin TDNn/BPVIn is used as BPVI input. A low-to-high transition on this pin inserts a bipolar violation on the next available mark in the transmit data stream. Sampling occurs on the falling edge of TCLK. But in TAOS with analog loopback mode, remote loopback mode and inband loopback mode, the BPVI is disabled. In TAOS with digital loopback mode, the BPVI is looped back to system side, so the data to be transmitted on TTINGn and TRINGn are all ones with no bipolar violation. JITTER ATTENUATOR The jitter attenuator is provided for narrow-band width jitter transfer and can be selected to work either in transmit path or in receive path or not used. The selection is accomplished by setting pin JAS in hardware mode or configuring bits JACF1 and JACF0 in register GCF in host mode which are both effected to all eight channels. For applications which require line synchronization, the line clock is need to be extracted for the internal synchronization, the jitter attenuator is set in the receive path. Another use of the jitter attenuator is to provide clock smoothing in the transmit path for applications such as synchronous/asynchronous demultiplexing applications. In these applications, TCLK will have an instantaneous frequency that is higher than the nominal T1/E1 data rate and in order to set the average long-term TCLK frequency within the transmit line rate specifications, periods of TCLK are suppressed (gapped). The jitter attenuator integrates a FIFO which can accommodate a gapped TCLK. In host mode, the FIFO length can be 32 X 2 or 64 X 2 bits by programming bit JADP in GCF. In hardware mode, it is fixed to 64 X 2 bits. The FIFO length determines the maximum permissible gap width (see table-8), exceeding these values will cause FIFO overflow or underflow. The data is 16 or 32 bits' delay through the jitter attenuator in the corresponding transmit or receive path. The constant delay feature is crucial for the applications requiring "hitless" switching. In host mode, bit JABW in GCF determines the jitter attenuator 3dB corner frequency (fc) for both T1 and E1. In hardware mode, the fc is fixed to 2.5Hz for T1 or 1.7Hz for E1. Generally, the lower the fc is, the higher the attenuation. However, lower fc comes at the expense of increased acquisition time. Therefore, the optimum fc is to optimize both the attenuation and the acquisition time. In addition, the longer FIFO length results in an increased throughput delay and also influences the 3dB corner frequency. Generally, it's recommended to use the lower
Figure - 10. DSX-1 Waveform Template
1.20
1.00
0.80 Normalized Amplitude
0.60
0.40
0.20
0.00
-0.20
-300
-200
-100
0 Time (ns)
100
200
300
Figure - 11. CEPT Waveform Template
TABLE - 7. BUILT-IN WAVEFORM TEMPLATE SELECTION
TS2 0 0 0 0 1 1 1 1 TS1 0 0 1 1 0 0 1 1 TS0 0 1 0 1 0 1 0 1 Service E1 Clock Rate 2.048 MHz Cable Length 120 / 75 Cable Reserved 1.544 MHz 0 133 266 399 533 133ft. ABAM 266ft. ABAM 399ft. ABAM 533ft. ABAM 655ft. ABAM 0.6 1.2 1.8 2.4 3.0 Maximum Cable Loss (dB) 1 -
T1
NOTE: 1. Maximum cable loss at 772 KHz
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
corner frequency and the shortest FIFO length that can still meet jitter attenuation requirements. TABLE - 8. GAP WIDTH LIMITATION
FIFO Length 64 bit 32 bit Max. Gap Width 56 UI 28 UI
LINE INTERFACE CIRCUITRY The transmit and receive interface RTIP/RRING and TTIP/TRING connections provide a matched interface to the cable. Figure-12 shows the appropriate external components to connect with the cable for one transmit/receive channel. Table-11 summarizes the component values based on the specific application. TRANSMIT DRIVER POWER SUPPLY All transmit driver power supplies must be 5.0V or 3.3V. In E1 mode, despite of the power supply voltage, the 75/120 lines are driven through 9.5 series resistors and a 1:2 transformer. In T1 mode, when 5.0V is selected, 100 lines are driven through 9.1 series resistors and a 1:2 transformer. When 3.3V, 100 lines are driven through a 1:2 transformer. To optimize the power consumption of the device, series resistors are removed in this case. However, in harsh cable environment, series resistors are required to improve the transmit return loss performance and protect the device from surges coupling into the device.
TABLE - 9. OUTPUT JITTER SPECIFICATION
T1 AT&T Pub 62411 GR-253-CODE TR-TSY-000009 E1 ITU-T G.736 ITU-T G.742 ITU-T G.783 ETSI CTR 12/13
TABLE - 10. TRANSFORMER SPECIFICATIONS
Electrical Specification @ 25 C Part No. Turns Ratio (Pri: sec2%) OCL @ 25C (mH MIN) LL (H MAX) STD Temp. EXT Temp. Transmit Receive Transmit Receive Transmit Receive T1124 T1114 1:2CT 1CT:2 1.2 1.2 .6 .6 TABLE - 11. EXTERNAL COMPONENTS VALUES Component RT RR Cp D1 - D4
CW/W (pF MAX) Transmit Receive 35 35
Package/ Schematic TOU/3
75 Coax 9.5 1% 9.31 1%
T1 120 Twisted Pair 100 Twisted Pair VDDT = 5.0V 100 Twisted Pair VDDT = 3.3V 9.5 1% 9.1 1% 0 15 1% 12.4 1% 12.4 1% 2200pf 1000pf Nihon Inter Electronics - EP05Q03L, 11EQS03L, EC10QS04, EC10QS03L; Motorola - MBR0540T1
E1
A
RX Line
2:1 ** 0.22F
1
One of Eight Identical Channels *
*
1k RR
RTIPn
B
2:1 ** TX Line Cp
1
*
1k RT
VDDT D4 D3
RRINGn * TTIPn
IDT82V2048
RR
VDDDn
VDDT * 0.1F
2
68F3
VDDT D2 RT D1
GNDTn * TRINGn
*
NOTE: 1. Pulse T1124 transformer is recommended to use in Standard (STD) operating temperature range (0 to 70C), while Pulse T1114 transformer is recommended to use in Extended (EXT) operating temperature range is -40 to +85C. See Transformer Specifications Table for details. 2. Typical value. Adjust for actual board parasitics to obtain optimum return loss. 3. Common decoupling capacitor for all VDDT and GNDT pins.
Figure - 12. External Transmit/Receive Line Circuitry
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
POWER DRIVER FAILURE MONITOR An internal power Driver Failure Monitor (DFM), parallelly connected with TTIPn and TRINGn, can detect short circuit failure in the secondary side of transformer. This feature is available only in host mode with no transmit series resistors, i.e. in T1 mode with VDDT is 3.3V. Bit SCPB in Register GCF decides whether the output driver shortcircuit protection is enabled. (Refer to Programming Information). When it is enabled, the max driver's output current is limited to 150mA. LINE PROTECTION In transmit side, the Schottky diodes D1~D4 are required to protect the line driver and improve the design robustness. In receive side, the series resistors of 1k are used to protect the receiver against current surges coupled in the device. It does not affect the receiver sensitivity, since the receiver impedance is as high as 120k typically. HITLESS PROTECTION SWITCHING (HPS) The IDT82V2048 tranceivers include an output driver tristatability feature for T1/E1 redundancy applications. This feature greatly reduces the cost of implementing redundancy protection by eliminating external relays. Details of HPS will be described in relative Application Note. RESET Writing register RS can cause software reset by initiating about 1s reset cycle. This operation set all the registers to their default value. POWER UP During power up, an internal reset signal sets all the registers to default values. This procedure takes at least 2 machine cycles. POWER DOWN Each transmitter channel will be power down by pulling pin TCLKn to low for more than 64 MCLK cycles (if MCLK is available) or about 30us (when MCLK is not availabe). Each transmitter channel will also be power down by setting bit TPDNn in e-TPDN to 1. All the receivers will power down when MCLK is Low. When MCLK is clocked or High, setting bit RPDNn in e-RPDN to `1' will configure the corresponding receiver to power down. INTERFACE WITH 5V LOGIC The IDT82V2048 can interface directly with 5V TTL family devices. The internal input pads are tolerant to 5V output from TTL and CMOS family devices. LOOPBACK MODE The device provides five different diagnostic loopback configurations: Digital Loopback, Analog Loopback, Remote Loopback, Dual Loopback and Inband Loopback. In host mode, these functions are implemented by programming the registers DLB, ALB, RLB or Inband Loopback register group. In hardware mode, only analog loopback and remote loopback can be selected by pulling pin LPn to High and Low respectively. Digital Loopback By programming the bits of register DLB, each channel of the device can be set in Local Digital Loopback. In this configuration, the data and clock to be transmitted, after passing the encoder, is looped back to jitter attenuator (if enabled) and decoder in the receive path, then output on
20
RCLKn, RDn/RDPn and CVn/RDNn. The data to be transmitted are still output on TTIPn and TRINGn while the data received on RTIPn and RRINGn are ignored. The Loss Detector is still in use. Figure-13 shows the process. Analog Loopback By programming the bits of ALB register or pulling pin LPn to High, each channel of the device can be set in Analog Loopback. In this configuration, the data to be transmitted output from the line driver are internally looped back to the slicer and peak detector in the receive path and output on RCLKn, RDn/RDPn and CVn/RDNn. The data to be transmitted are still output on TTIPn and TRINGn while the data received on RTIPn and RRINGn are ignored. The Loss Detector is still in use. Figure-14 shows the process. The TTIPn and RTIPn, TRINGn and RRINGn cannot be connected directly to do the external analog loopback test. Line impedance loading is required to connduct the external analog loopback test. Remote Loopback By programming the bits of RLB register or pulling pin LPn to Low, each channel of the device can be set in Remote Loopback. In this configuration, the data and clock recovered by the Clock and Data Recovery circuits are looped to waveform shaper and output on TTIPn and TRINGn. The jitter attenuator is also included in loopback when enabled in the transmit or receive path. The received data and clock are still output on RCLKn, RDn/RDPn and CVn/RDNn while the data to be transmitted on TCLKn, TDn/TDPn and BPVIn/TDNn are ignored. The Loss Detector is still in use. Figure-15 shows the process. Dual Loopback Dual Loopback mode is set by setting both bit DLBn in register DLB and bit RLBn in register RLB to `1'. In this configuration, after passing the encoder, the data and clock to be transmitted are looped back to decoder directly and output on RCLKn, RDn/RDPn and CVn/RDNn. The recovered data from RTIPn and RRINGn are looped back to waveform shaper through JA (if selected) and output on TTIPn and TRINGn. The Loss Detector is still in use. Figure-16 shows the process. Transmit All Ones In hardware mode, the TAOS mode is set by pulling TCLKn High for more than 16 MCLK cycles. In host mode, TAOS mode is set by programming register TAO. In addition, automatic TAO signals are inserted by setting register ATAO when Loss of Signal occurs. Note that the TAOS generator adopts MCLK as a timing reference. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability. This TAOS mode and Digital Loopback or Analog Loopback can be configured simultaneously. Figure-17 shows their process.
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
LOS Detector RTIPn RRINGn Peak Detector TTIPn TRINGn Line Driver Waveform Shaper Transmit All Ones Slicer CLK&Data Recovery (DPLL)
One of Eight Identical Channels LOSn Jitter Attenuator Digital Loopback Jitter Attenuator B8ZS/ HDB3/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn B8ZS/ HDB3/AMI Decoder RCLKn RDn/RDPn CVn/RDNn
Figure - 13. Digital Loopback
One of Eight Identical Channels LOSn Jitter Attenuator B8ZS/ HDB3/AMI Decoder RCLKn RDn/RDPn CVn/RDNn
LOS Detector RTIPn RRINGn Analog Loopback TTIPn TRINGn Peak Detector Line Driver Waveform Shaper Transmit All Ones Slicer CLK&Data Recovery (DPLL)
Jitter Attenuator
B8ZS/ HDB3/AMI Encoder
TCLKn TDn/TDPn BPVIn/TDNn
Figure - 14. Analog Loopback
One of Eight Identical Channels LOSn Jitter Attenuator Remote/ Inband Loopback Line Driver Waveform Shaper Transmit All Ones Jitter Attenuator B8ZS/ HDB3/AMI Encoder IBLC Generator B8ZS/ HDB3/AMI Decoder IBLC Detector RCLKn RDn/RDPn CVn/RDNn
LOS Detector RTIPn RRINGn Peak Detector TTIPn TRINGn Slicer CLK&Data Recovery (DPLL)
TCLKn TDn/TDPn BPVIn/TDNn
Figure - 15. Remote Loopback
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One of Eight Identical Channels LOSn Jitter Attenuator B8ZS/ HDB3/AMI Decoder RCLKn RDn/RDPn CVn/RDNn
LOS Detector RTIPn RRINGn Peak Detector TTIPn TRINGn Line Driver Waveform Shaper Transmit All Ones Slicer CLK&Data Recovery (DPLL)
Jitter Attenuator
B8ZS/ HDB3/AMI Encoder
TCLKn TDn/TDPn BPVIn/TDNn
Figure - 16. Dual Loopback
LOS Detector RTIPn RRINGn Peak Detector TTIPn TRINGn Line Driver Waveform Shaper Transmit All Ones Jitter Attenuator B8ZS/ HDB3/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn Slicer CLK&Data Recovery (DPLL) One of Eight Identical Channels LOSn Jitter Attenuator B8ZS/ HDB3/AMI Decoder RCLKn RDn/RDPn CVn/RDNn
Figure - 17a. TAOS Data Path
One of Eight Identical Channels LOSn Jitter Attenuator B8ZS/ HDB3/AMI Decoder RCLKn RDn/RDPn CVn/RDNn
LOS Detector RTIPn RRINGn Peak Detector TTIPn TRINGn Line Driver Waveform Shaper Transmit All Ones Slicer CLK&Data Recovery (DPLL)
Jitter Attenuator
B8ZS/ HDB3/AMI Encoder
TCLKn TDn/TDPn BPVIn/TDNn
Figure - 17b. TAOS with Digital Loopback
22
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
LOS Detector RTIPn RRINGn Peak Detector TTIPn TRINGn Line Driver Waveform Shaper Transmit All Ones Slicer CLK&Data Recovery (DPLL)
INDUSTRIAL TEMPERATURE RANGES
One of Eight Identical Channels LOSn Jitter Attenuator B8ZS/ HDB3/AMI Decoder RCLKn RDn/RDPn CVn/RDNn
B8ZS/ HDB3/AMI Encoder
TCLKn TDn/TDPn BPVIn/TDNn
Figure - 17c. TAOS with Analog Loopback Inband Loopback Inband Loopback is a function that facilitates the system remote diagnosis. When this function is enabled, the chip will detect or generate the Inband Loopback Code. There are two kinds of Inband Loopback Code:Active Code and Deactive Code. If the Active Code is received from the far end in a continuous 5.1 second, the chip can go into Remote Loopback Mode (Figure-15) automatically. If the Deactive Code is received from the far end in a continuous 5.1 second, the chip can quit from the Remote Loopback mode automatically. The chip can also send the Active Code and Deactive Code to the far end. Two function blocks realize the Inband Loopback : IBLC Detector (Inband Loopback Code Detector) and IBLC Generator ( Inband Loopback Code Generator). The detection of Inband Loopback Code is enabled by LBDE (bit 5, e-LBCF register). If ALBE (bit 4, e-LBCF register) is set to 1, the chip will go into or quit from the Remote Loopback mode automatically based on the receipt of Inband Loopback Code. The length of the Active Code is defined in LBAL[1:0] (bit 3-2, e-LBCF register); and the length of the Deactive Code is defined in the LBDL[1:0] (bit 1-0, e-LBCF register). The pattern of the Active Code is defined in the e-LBAC register, and the pattern of the Deactive Code is defined in the e-LBDC register. The above settings are globally effective for all the eight channels. The presence of Inband Loopback Code in each channel is reflected timely in the e-LBS register. Any transition of each bit in the e-LBS register will be reflected in the e-LBI register, and if enabled in the e-LBM register, will generate an interrupt. The required sequence of programming the Inband Loopback Code detection is : First, set the e-LBAC and eLBDC registers, followed by the e-LBM register. Finally, to activate Inband Loopback detection, set the e-LBCF register. The Inband Loopback Code Generator use the same registers as the Inband Loopback Detector to define the length and pattern of Active Code and Deactive Code. The length and pattern of the generated Active Code and Deactive Code can be different from the detected Active Code and Deactive Code. The e-LBGS register determines sending Active Code or Deactive Code, and the e-LBGE acts as a switch button to start or stop the sending of Inband Loopback Code to the selected channels. Before sending Inband Loopback Code, users should be sure that the e-LBCF register, the e-LBAC register, the e-LBDC register and the e-LBSG register are configured properly. The required sequence for configuring the Inband Loopback Generator is: First, set the e-LBAC and e-LBDC registers, followed by the e-LBCF register. Then, to select the Inband Loopback generator set e-LBGS and then e-LBGE. The Inband Loopback Detection and the Inband Loopback Genera23
tion can not be used simultaneously. Example: 5-bit Loop-up/Loop-Down Detection (w/o interrupts): (see note in register description for e-LBAC) Loop-up code: 11000 Loop-down code : 11100 Set (in this order) e-LBAC (0x09) = 0xC6 (11000110) e-LBDC (0x0A) = 0xE7 (11100111) e-LBCF (0x08) = 0x30 Example: 5-bit Loop-up/Loop-down Activation on Channel 1 (w/o interrupts): Loop-up code: 11000 Loop-down code : 11100 Set (in this order) e-LBAC (0x09) = 0xC6 (11000110) e-LBDC (0x0A) = 0xE7 (11100111) e-LBCF (0x08) = 0x00 e-LBGS (0x0E) = 0x00 e-LBGE (0x0F) = 0x02 HOST INTERFACES The host interface provides access to read and write the registers in the device. The interface consists of serial host interface and parallel host interface. By pulling pin MODE2 to VDDIO/2 or to High, the device can be set to work in serial mode and in parallel mode respectively. Parallel Host Interface The interface is compatible with Motorola or Intel host. Pins MODE1 and MODE0 are used to select the operating mode of the parallel host interface. When pin MODE1 is pulled to Low, the host uses separate address bus and data bus. When High, multiplexed address/data bus is used. When pin MODE0 is pulled to Low, the parallel host interface is configured for Motorola compatible hosts. When High, for Intel compatible hosts. This is well described in the Pin Description. The host interface pins in each operation mode is tabulated in Table-12.
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 12. PARALLEL HOST INTERFACE PINS MODE[2:0] 100 101 110 111 Host interface Non-multiplexed Motorola interface Non-multiplexed Intel interface Multiplexed Motorola interface Multiplexed Intel interface
CS SCLK SDI
1 R/W A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 2 2
Generic control, data, and output pin name CS, ACK, DS, R/W, AS, A[4:0], D[7:0], INT CS, RDY, WR, RD, ALE, A[4:0], D[7:0], INT CS, ACK, DS, R/W, AS, AD[7:0], INT CS, RDY, WR, RD, ALE, AD[7:0], INT
Address/Command Byte SDO High Impedance
Input Data Byte D0 D1 D2 D3 D4 D5 D6 D7 Driven while R/W=1
NOTE: 1. While R/W=1, read from IDT82V2048; While R/W=0, write to IDT82V2048. 2. Ignored.
Figure - 18. Serial Host Mode Timing
Serial Host Interface By pulling pin MODE2 to VDDIO/2, the device operates in the serial host Mode. In this mode, the registers are accessible through a 16-bit word which contains an 8-bit command/address byte (bit R/W and 5address-bit A1~A5, A6 and A7 are ignored) and a subsequent 8-bit data byte (D0~D7). When bit R/W is 1, data is read out at pin SDO. When bit R/W is 0, data is written into pin SDI to the register which is indicated by address bits A5~A1.
No
Interrupt Allowed
INTERRUPT HANDLING Interrupt Sources There are four kinds of interrupt sources: 1. Status change in the LOS (Loss of Signal) Status Register(04H). The analog/digital loss of signal detector continuously monitors the received signal to update the specific bit in LOS which indicates presence or absence of a LOS condition. 2. Status change in the DF (Driver Fault) Status Register(05H). The automatic power driver circuit continuously monitors the output drivers signal to update the specific bit in DFM which indicates presence or absence of a secondary driver short circuit condition. 3. Status change in the AIS (Alarm Indication Signal) Status Register(13H). The AIS detector monitors the received signal to update the specific bit in AIS which indicates presence or absence of a AIS condition. 4. Status change in the e-LBS (Inband Loopback Code Receive) Status Register, (expanded 0BH). The IBLC detector monitors the inband loopback activation or deactivation code in received signal to update the specific bit in e-LBS which indicates presence or absence of an inband loopback condition.
Interrupt Condition Exist? Yes
Read Interrupt Status Register
Read Corresponding Status Register
Service the Interrupt
Figure - 19. Interrupt Service Routine
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Interrupt Enable The IDT82V2048 provides a latched interrupt output (INT) and the four kinds of interrupts are all reported by this pin. When the Interrupt Mask register (LOSM , DFM, AISM and e-LBM) is set to `1', the Interrupt Status register (LOSI, DFI, AISI and e-LBI) is enabled respectively. Whenever there is a transition (`0' to `1' or `1' to `0') in the corresponding Status register, the Interrupt Status register will change into `1', which means an interrupt occurs, and there will be a transition from high to low on INT. An external pull-up resistor of approximately 10k is required to support the wire-OR operation of INT. When any of the four Interrupt Mask registers is set to `0' (the power-on default value is `0'), the corresponding Interrupt Status register is disabled and the transition on status register is ignored. Interrupt Clearing When an interrupt occurs, the Interrupt Status registers (LOSI, DFI, AISI and e-LBI) are read to identify the interrupt source. And these registers will be cleared to `0' after the corresponding Status register (LOS, DF, AIS and e-LBS) being read. The Status registers will be cleared once the corresponding conditions are met. Pin INT is pulled High when there are no pending interrupt left. The interrupt handling in the interrupt service routine is showed Figure-19.
G.772 MONITORING The eight channels of IDT82V2048 can all be configured to work as regular transceivers. In applications using only seven channels (channels 1 to 7), channel 0 is configured to non-intrusively monitor any of the other channels' inputs or outputs on the line side. The monitoring is non-intrusive per ITU-T G.772. Figure-20 shows the Monitoring Principle. The receiver or transmitter path to be monitored is configured by pin MC[0:3] in hardware mode or by PMON in host mode (refer to Programming Information for details). The signal which is monitored goes through the clock and data recovery circuit of channel 0. The monitored clock can output on RCLK0 which can be used as a timing interfaces derived from E1 signal. The monitored data can be observed digitally at the output pin RCLK0, RD0/RDP0 and RDN0. LOS detector is still in use in channel 0 for the monitored signal. In monitoring mode, channel 0 can be configured to the Remote Loopback. The signal which is being monitored will output on TTIP0 and TRING0. The output signal can then be connected to a standard test equipment with an E1 electrical interface for non-intrusive monitoring.
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Channel N ( 7 > N > 1 ) LOS Detector RTIPn RRINGn Peak Detector TTIPn TRINGn Line Driver Waveform Shaper Transmit All Ones Jitter Attenuator B8ZS/ HDB3/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn Slicer CLK&Data Recovery (DPLL) Jitter Attenuator B8ZS/ HDB3/AMI Decoder LOSn RCLKn RDn/RDPn CVn/RDNn
G.772 Monitor RTIP0 RRING0 Peak Detector TTIP0 TRING0 Line Driver
Channel 0 LOS Detector Slicer CLK&Data Recovery (DPLL) Jitter Attenuator B8ZS/ HDB3/AMI Decoder Remote Loopback Waveform Shaper Transmit All Ones Jitter Attenuator B8ZS/ HDB3/AMI Encoder TCLK0 TD0/TDP0 BPVI0/TDN0 LOS0 RCLK0 RD0/RDP0 CV0/RDN0
Figure - 20. Monitoring Principle
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PROGRAMMING INFORMATION
REGISTER LIST AND MAP There are 23 primary registers (including an Address Pointer Control Register), including 16 expanded registers in the device. Whatever the control interface is, 5 address bits are used to set the registers. In non-multiplexed parallel interface mode, the five dedicated address bits are A[4:0]. In multiplexed parallel interface mode, AD[4:0] carries the address information. In serial interface mode, A[5:1] are used TABLE - 13. PRIMARY REGISTER LIST
Address serial parallel interface interface A7-A1 A7-A0 XX00000 XXX00000 XX00001 XXX00001 XX00010 XXX00010 XX00011 XXX00011 XX00100 XXX00100 XX00101 XXX00101 XX00110 XXX00110 XX00111 XXX00111 XX01000 XXX01000 XX01001 XXX01001 XX01010 XXX01010 XX01011 XXX01011 XX01100 XXX01100 XX01101 XXX01101 XX01110 XXX01110 XX01111 XXX01111 XX10000 XXX10000 XX10001 XXX10001 XX10010 XXX10010 XX10011 XXX10011 XX10100 XXX10100 XX10101 XXX10101 XX10110 XXX10110 XX10111 XXX10111 XX11000 XXX11000 XX11001 XXX11001 XX11010 XXX11010 XX11011 XXX11011 XX11100 XXX11100 XX11101 XXX11101 XX11110 XXX11110 XX11111
to address the register.
T eA d e sP i e C n rlRegitr DDP), addressed as 11111 or h d r s ontr o to seA ( 1F Hex, switches between primary registers bank and expanded registers bank. By setting the content of ADDP to AAH, the 5 address bits point to the expanded register bank, that is, 16 expanded registers are then available to access. By clearing ADDP, the primary registers are accessible again.
Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
Register ID ALB RLB TAO LOS DF LOSM DFM LOSI DFI RS PMON DLB LAC ATAO GCF TSIA TS OE AIS AISM AISI
R/W R R/W R/W R/W R R R/W R/W R R W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R
Explanation Device ID Register Analog Loopback Configuration Register Remote Loopback Configuration Register Transmit All One Code Configuration Register Loss of Signal Status Register Driver Fault Status Register LOS Interrupt Mask Register Driver Fault Interrupt Mask Register LOS Interrupt Status Register Driver Fault Interrupt Status Register Software Reset Register Performance Monitor Configuration Register Digital Loopback Configuration Register LOS/AIS Criteria Configuration Register Automatic TAO Configuration Register Global Configuration Register Indirect Address Register for Transmit Template Select Transmit Template Select Register Output Enable Configuration Register AIS Status Register AIS Interrupt Mask Register AIS Interrupt Status Register
Reserved
XXX11111 ADDP
R/W
Address pointer control Register for switching between primary register bank and expanded register bank
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TABLE - 14. EXPANDED (INDIRECT ADDRESS MODE) REGISTER LIST
Address serial Hex interface A7-A1 00 XX00000 01 XX00001 02 XX00010 03 XX00011 04 XX00100 05 XX00101 06 XX00110 07 XX00111 08 XX01000 09 XX01001 0A XX01010 0B XX01011 0C XX01100 0D XX01101 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F XX01110 XX01111 XX10000 XX10001 XX10010 XX10011 XX10100 XX10101 XX10110 XX10111 XX11000 XX11001 XX11010 XX11011 XX11100 XX11101 XX11110 XX11111 parallel interface A7-A0 XXX00000 XXX00001 XXX00010 XXX00011 XXX00100 XXX00101 XXX00110 XXX00111 XXX01000 XXX01001 XXX01010 XXX01011 XXX01100 XXX01101 Register e-SING e-CODE e-CRS e-RPDN e-TPDN e-CZER e-CODV e-EQUA e-LBCF e-LBAC e-LBDC e-LBS e-LBM e-LBI R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R Explanation
XXX01110 e-LBGS XXX01111 e-LBGE XXX10000 XXX10001 XXX10010 XXX10011 XXX10100 XXX10101 XXX10110 XXX10111 XXX11000 XXX11001 XXX11010 XXX11011 XXX11100 XXX11101 XXX11110 XXX11111 ADDP
Single Rail Mode Setting Register Encoder/Decoder Selection Register Clock Recovery Enable/Disable Register Receiver n Powerdown Enable/Disable Register Transmitter n Powerdown Enable/Disable Register Consecutive Zero Detect Enable/Disable Register Code Violation Detect Enable/Disable Register Enable Equalizer Enable/Disable Register Inband Loopback Configuration Register Inband Loopback Activation Code Register Inband Loopback Deactivation Code Register Inband Loopback Code Receive Status Register Inband Loopback Interrupt Mask Register Inband Loopback Interrupt Status Register Inband Loopback Activation/Deactivation Code Generator R/W Selection Register Inband Loopback Activation/Deactivation Code Generator R/W Enable Register
Test
R/W
Address pointer control register for switching between primary register bank and expanded register bank
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TABLE - 15. PRIMARY REGISTER MAP
Address R/W b7 Default 00 Hex ID 7 R/W R Default 0 01 Hex ALB 7 R/W R/W 0 Default 02 Hex RLB 7 R/W R/W Default 0 03 Hex TAO 7 R/W R/W Default 0 04 Hex LOS 7 R/W R 0 Default 05 Hex DF 7 R/W R 0 Default 06 Hex LOSM 7 R/W R/W Default 0 07 Hex DFM 7 R/W R/W 0 Default 08 Hex LOSI 7 R R/W 0 Default 09 Hex DFI 7 R R/W 0 Default 0A Hex RS 7 W W Default 1 0B Hex R/W R/W Default 0 0C Hex DLB 7 R/W R/W Default 0 0D Hex LAC 7 R/W R/W Default 0 0E Hex ATAO 7 R/W R/W Default 0 0F Hex R/W R/W Default 0
Register ID ALB RLB TAO LOS DF LOSM DFM LOSI DFI RS PMON DLB LAC ATAO GCF
b6 ID 6 R 0 ALB 6 R/W 0 RLB 6 R/W 0 TAO 6 R/W 0 LOS 6 R 0 DF 6 R 0 LOSM 6 R/W 0 DFM 6 R/W 0 LOSI 6 R 0 DFI 6 R 0 RS 6 W 1 R/W 0 DLB 6 R/W 0 LAC 6 R/W 0 ATAO 6 R/W 0 AISE R/W 0
b5 ID 5 R 0 ALB 5 R/W 0 RLB 5 R/W 0 TAO 5 R/W 0 LOS 5 R 0 DF 5 R 0 LOSM 5 R/W 0 DFM 5 R/W 0 LOSI 5 R 0 DFI 5 R 0 RS 5 W 1 R/W 0 DLB 5 R/W 0 LAC 5 R/W 0 ATAO 5 R/W 0 SCPB R/W 0
b4 ID 4 R 1 ALB 4 R/W 0 RLB 4 R/W 0 TAO 4 R/W 0 LOS 4 R 0 DF 4 R 0 LOSM 4 R/W 0 DFM 4 R/W 0 LOSI 4 R 0 DFI 4 R 0 RS 4 W 1 R/W 0 DLB 4 R/W 0 LAC 4 R/W 0 ATAO 4 R/W 0 CODE R/W 0
b3 ID 3 R 0 ALB 3 R/W 0 RLB 3 R/W 0 TAO 3 R/W 0 LOS 3 R 0 DF 3 R 0 LOSM 3 R/W 0 DFM 3 R/W 0 LOSI 3 R 0 DFI 3 R 0 RS 3 W 1 MC 3 R/W 0 DLB 3 R/W 0 LAC 3 R/W 0 ATAO 3 R/W 0 JADP R/W 0
b2 ID 2 R 0 ALB 2 R/W 0 RLB 2 R/W 0 TAO 2 R/W 0 LOS 2 R 0 DF 2 R 0 LOSM 2 R/W 0 DFM 2 R/W 0 LOSI 2 R 0 DFI 2 R 0 RS 2 W 1 MC 2 R/W 0 DLB 2 R/W 0 LAC 2 R/W 0 ATAO 2 R/W 0 JABW R/W 0
b1 ID 1 R 0 ALB 1 R/W 0 RLB 1 R/W 0 TAO 1 R/W 0 LOS 1 R 0 DF 1 R 0 LOSM 1 R/W 0 DFM 1 R/W 0 LOSI 1 R 0 DFI 1 R 0 RS 1 W 1 MC 1 R/W 0 DLB 1 R/W 0 LAC 1 R/W 0 ATAO 1 R/W 0 JACF 1 R/W 0
b0 ID 0 R 0 ALB 0 R/W 0 RLB 0 R/W 0 TAO 0 R/W 0 LOS 0 R 0 DF 0 R 0 LOSM 0 R/W 0 DFM 0 R/W 0 LOSI 0 R 0 DFI 0 R 0 RS 0 W 1 MC 0 R/W 0 DLB 0 R/W 0 LAC 0 R/W 0 ATAO 0 R/W 0 JACF 0 R/W 0
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TABLE - 15. PRIMARY REGISTER MAP (CONTINUED)
Register Address R/W b7 Default 10 Hex R/W R/W Default 0 11 Hex R/W R/W Default 0 12 Hex OE 7 R/W R/W 0 Default 13 Hex AIS 7 R/W R Default 0 14 Hex AISM 7 R/W R/W Default 0 15 Hex AISI 7 R/W R 0 Default 1F Hex ADDP 7 R/W R/W 0 Default b6 b5 b4 b3 b2 b1 b0
TSIA TS OE AIS AISM AISI ADDP
R/W 0 R/W 0 OE 6 R/W 0 AIS 6 R 0 AISM 6 R/W 0 AISI 6 R 0 ADDP 6 R/W 0
R/W 0 R/W 0 OE 5 R/W 0 AIS 5 R 0 AISM 5 R/W 0 AISI 5 R 0 ADDP 5 R/W 0
R/W 0 R/W 0 OE 4 R/W 0 AIS 4 R 0 AISM 4 R/W 0 AISI 4 R 0 ADDP 4 R/W 0
R/W 0 R/W 0 OE 3 R/W 0 AIS 3 R 0 AISM 3 R/W 0 AISI 3 R 0 ADDP 3 R/W 0
TSIA 2 R/W 0 TS 2 R/W 0 OE 2 R/W 0 AIS 2 R 0 AISM 2 R/W 0 AISI 2 R 0 ADDP 2 R/W 0
TSIA 1 R/W 0 TS 1 R/W 0 OE 1 R/W 0 AIS 1 R 0 AISM 1 R/W 0 AISI 1 R 0 ADDP 1 R/W 0
TSIA 0 R/W 0 TS 0 R/W 0 OE 0 R/W 0 AIS 0 R 0 AISM 0 R/W 0 AISI 0 R 0 ADDP 0 R/W 0
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TABLE - 16. EXPANDED (INDIRECT ADDRESS MODE) REGISTER MAP
Register e-SING e-CODE e-CRS e-RPDN e-TPDN e-CZER e-CODV e-EQUA e-LBCF e-LBAC e-LBDC e-LBS e-LBM e-LBI e-LBGS e-LBGE Address R/W Default 00 Hex R/W Default 01 Hex R/W Default 02 Hex R/W Default 03 Hex R/W Default 04 Hex R/W Default 05 Hex R/W Default 06 Hex R/W Default 07 Hex R/W Default 08 Hex R/W Default 09 Hex R/W Default 0A Hex R/W Default 0B Hex R Default 0C Hex R/W Default 0DHex R/W Default 0E Hex R/W Default 0F Hex R/W Default 1F Hex R/W Default b7 SING 7 R/W 0 CODE 7 R/W 0 CRS 7 R/W 0 RPDN 7 R/W 0 TPDN 7 R/W 0 CZER 7 R/W 0 CODV 7 R/W 0 EQUA 7 R/W 0 R/W 0 LBAC 7 R/W 0 LBDC 7 R/W 0 LBS 7 R 0 LBM 7 R/W 0 LBI 7 R 0 LBGS 7 R/W 0 LBGE 7 R/W 0 ADDP 7 R/W 0 b6 SING 6 R/W 0 CODE 6 R/W 0 CRS 6 R/W 0 RPDN 6 R/W 0 TPDN 6 R/W 0 CZER 6 R/W 0 CODV 6 R/W 0 EQUA 6 R/W 0 R/W 0 LBAC 6 R/W 0 LBDC 6 R/W 0 LBS 6 R 0 LBM 6 R/W 0 LBI 6 R 0 LBGS 6 R/W 0 LBGE 6 R/W 0 ADDP 6 R/W 0 b5 SING 5 R/W 0 CODE 5 R/W 0 CRS 5 R/W 0 RPDN 5 R/W 0 TPDN 5 R/W 0 CZER 5 R/W 0 CODV 5 R/W 0 EQUA 5 R/W 0 LBDE R/W 0 LBAC 5 R/W 0 LBDC 5 R/W 0 LBS 5 R 0 LBM 5 R/W 0 LBI 5 R 0 LBGS 5 R/W 0 LBGE 5 R/W 0 ADDP 5 R/W 0 b4 SING 4 R/W 0 CODE 4 R/W 0 CRS 4 R/W 0 RPDN 4 R/W 0 TPDN 4 R/W 0 CZER 4 R/W 0 CODV 4 R/W 0 EQUA 4 R/W 0 ALBE R/W 0 LBAC 4 R/W 0 LBDC 4 R/W 0 LBS 4 R 0 LBM 4 R/W 0 LBI 4 R 0 LBGS 4 R/W 0 LBGE 4 R/W 0 ADDP 4 R/W 0 b3 SING 3 R/W 0 CODE 3 R/W 0 CRS 3 R/W 0 RPDN 3 R/W 0 TPDN 3 R/W 0 CZER 3 R/W 0 CODV 3 R/W 0 EQUA 3 R/W 0 LBAL 1 R/W 0 LBAC 3 R/W 0 LBDC 3 R/W 0 LBS 3 R 0 LBM 3 R/W 0 LBI 3 R 0 LBGS 3 R/W 0 LBGE 3 R/W 0 ADDP 3 R/W 0 b2 SING 2 R/W 0 CODE 2 R/W 0 CRS 2 R/W 0 RPDN 2 R/W 0 TPDN 2 R/W 0 CZER 2 R/W 0 CODV 2 R/W 0 EQUA 2 R/W 0 LBAL 0 R/W 0 LBAC 2 R/W 0 LBDC 2 R/W 0 LBS 2 R 0 LBM 2 R/W 0 LBI 2 R 0 LBGS 2 R/W 0 LBGE 2 R/W 0 ADDP 2 R/W 0 b1 SING 1 R/W 0 CODE 1 R/W 0 CRS 1 R/W 0 RPDN 1 R/W 0 TPDN 1 R/W 0 CZER 1 R/W 0 CODV 1 R/W 0 EQUA 1 R/W 0 LBDL 1 R/W 0 LBAC 1 R/W 0 LBDC 1 R/W 0 LBS 1 R 0 LBM 1 R/W 0 LBI 1 R 0 LBGS 1 R/W 0 LBGE 1 R/W 0 ADDP 1 R/W 0 b0 SING 0 R/W 0 CODE 0 R/W 0 CRS 0 R/W 0 RPDN 0 R/W 0 TPDN 0 R/W 0 CZER 0 R/W 0 CODV 0 R/W 0 EQUA 0 R/W 0 LBDL 0 R/W 0 LBAC 0 R/W 0 LBDC 0 R/W 0 LBS 0 R 0 LBM 0 R/W 0 LBI 0 R 0 LBGS 0 R/W 0 LBGE 0 R/W 0 ADDP 0 R/W 0
ADDP
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
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REGISTER DESCRIPTION Primary Register Description ID: Device ID Register (R, Address = 00 Hex)
Symbol ID[7:0] Position ID.7-0 Default 10 H Description An 8-bit word is pre-set into the device as the identification and revision number. This number is different with the functional changes and is mask programmed.
ALB: Analog Loopback Configuration Register (R/W, Address = 01 Hex)
Symbol ALB[7:0] Position ALB.7-0 Default 00 H 0 = Normal operation. (Default) 1 = Analog Loopback enabled. Description
RLB: Remote Loopback Configuration Register (R/W, Address = 02 Hex)
Symbol RLB[7:0] Position RLB.7-0 Default 00 H 0 = Normal operation. (Default) 1 = Remote Loopback enabled. Description
TAO: Transmit All One Code Configuration Register (R/W, Address = 03 Hex)
Symbol TAO[7:0] Position TAO.7-0 Default 00 H 0 = Normal operation. (Default) 1 = Transmit all one code. Description
LOS: Loss of Signal Status Register (R, Address = 04 Hex)
Symbol LOS[7:0] Position LOS.7-0 Default 00 H 0 = Normal operation. (Default) 1 = Loss of signal detected. Description
DF: Driver Fault Status Register (R, Address = 05 Hex)
Symbol DF[7:0] Position DF.7-0 Default 00 H Description 0 = Normal operation. (Default) 1 = Driver fault detected. Note that DF is available only in T1 mode with 3.3V (without transmit series resistors).
LOSM : Loss of Signal Interrupt Mask Register (R/W, Address = 06 Hex)
Symbol LOSM[7:0] Position LOSM.7-0 Default 00 H Description 0 = LOS interrupt is not allowed. (Default) 1 = LOS interrupt is allowed.
DFM: Driver Fault Interrupt Mask Register (R/W, Address = 07 Hex)
Symbol DFM[7:0] Position DFM.7-0 Default 00 H Description 0 = Driver fault interrupt is not allowed. (Default) 1 = Driver fault interrupt is allowed.
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LOSI: Loss of Signal Interrupt Status Register (R, Address = 08 Hex)
Symbol LOSI[7:0] Position LOSI.7-0 Default 00 H Description 0 = (Default). Or after a LOS read operation. 1 = Any transition on LOSn (Corresponding LOSMn is set to 1).
DFI: Driver Fault Interrupt Status Register (R, Address = 09 Hex)
Symbol DFI[7:0] Position DFI.7-0 Default 00 H Description 0 = (Default). Or after a DF read operation. 1 = Any transition on DFn (Corresponding DFMn is set to 1).
RS: Software Reset Register (W, Address = 0A Hex)
Symbol RS[7:0] Position RS.7-0 Default FF H Description Writing to this register will not change the content in this register but initiate a 1s reset cycle, which means all the registers in the device are set to their default values.
PMON: Performance Monitor Configuration Register (R/W, Address = 0B Hex)
Symbol Position PMON.7-4 Default 0000 Description 0 = Normal operation. (Default) 1 = Reserved. MC[3:0] Monitoring Configuration 0000 Normal operation without monitoring. 0001 Monitoring receiver 1. 0010 Monitoring receiver 2. 0011 Monitoring receiver 3. 0100 Monitoring receiver 4. 0101 Monitoring receiver 5. 0110 Monitoring receiver 6. 0111 Monitoring receiver 7. 1000 Normal operation without monitoring. 1001 Monitoring transmitter 1. 1010 Monitoring transmitter 2. 1011 Monitoring transmitter 3. 1100 Monitoring transmitter 4. 1101 Monitoring transmitter 5. 1110 Monitoring transmitter 6. 1111 Monitoring transmitter 7.
MC[3:0]
PMON.3-0
0000
DLB: Digital Loopback Configuration Register (R/W, Address = 0C Hex)
Symbol DLB[7:0] Position DLB.7-0 Default 00 H 0 = Normal operation. (Default) 1 = Digital Loopback enabled. Description
LAC: LOS/AIS Criteria Configuration Register (R/W, Address = 0D Hex)
Symbol LAC[7:0] Position LAC.7-0 Default 00 H Description For E1 mode, the criterion is selected as below: 0 = G.775 mode. (Default) 1 = ETSI 300233 mode. For T1 mode, the criterion meets T1.231.
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ATAO: Automatic TAO Configuration Register (R/W, Address = 0E Hex)
Symbol ATAO[7:0] Position ATAO.7-0 Default 00 H Description 0 = No automatic TAO. (Default) 1 = Automatic transmit all ones to the line side on LOS.
GCF: Global Configuration Register (R/W, Address = 0F Hex)
Symbol AISE SCPB CODE Position GCF.7 GCF.6 GCF.5 GCF.4 Default 0 0 0 0 Description 0 = Normal operation. (Default) 1 = Reserved. AIS Enable During LOS. 0 = AIS insertion to the system side disabled on LOS. (Default) 1 = AIS insertion to the system side enabled on LOS. Short Circuit Protection Enable. 0 = Short circuit protection is enabled. (Default) 1 = Short circuit protection is disabled. Line Code Enable. 0 = B8ZS/HDB3 encoder/decoder enabled. (Default) 1 = AMI encoder/decoder enabled. Jitter Attenuator Depth Select. JADP FIFO 0 32-bit (Default) 1 64-bit Jitter Transfer Function Bandwidth Select. JABW T1 E1 0 2.5Hz (Default) 1.7Hz (Default) 1 5Hz 6.5Hz Jitter Attenuator Configuration. JACF[1:0] Jitter Attenuator (JA) Configuration 00 JA not used. (Default) 01 JA in transmit path. 10 JA not used. 11 JA in receive path.
JADP
GCF.3
0
JABW
GCF.2
0
JACF[1:0]
GCF.1-0
00
TSIA: Indirect Address Register for Transmit Template Select Registers (R/W, Address = 10 Hex)
Symbol Position TSIA.7-3 Default 00000 0 = Normal operation. (Default) 1 = Reserved. TSIA[2:0] Channel 000 0 001 1 010 2 011 3 Description TSIA[2:0] 100 101 110 111 Channel 4 5 6 7
TSIA[2:0]
TSIA.2-0
000
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TS: Transmit Template Select Register (R/W, Address = 11 Hex)
Symbol Position TS.7-3 Default 00000 Description 0 = Normal operation. (Default) 1 = Reserved. TS[2:0] select one of eight built-in transmit template for different applications. TS[2:0] Mode Cable Length 000 E1 75 coaxial cable/120 twisted pair cable. 001 Reserved. 010 011 T1 0 - 133 ft. 100 T1 133 - 266 ft. 101 T1 266 - 399 ft. 110 T1 399 - 533 ft. 111 T1 533 - 655 ft.
TS[2-0]
TS.2-0
000
OE: Output Enable Configuration Register (R/W, Address = 12 Hex)
Symbol OE[7:0] Position OE.7-0 Default 00 H Description 0 = Transmit drivers enabled. (Default) 1 = Transmit drivers placed in high impedance state.
AIS: Alarm Indication Signal Status Register (R, Address = 13 Hex)
Symbol AIS[7:0] Position AIS.7-0 Default 00 H 0 = Normal operation. (Default) 1 = AIS detected. Description
AISM : Alarm Indication Signal Interrupt Mask Register (R/W, Address = 14 Hex)
Symbol AISM[7:0] Position AISM.7-0 Default 00 H Description 0 = AIS interrupt is not allowed. (Default) 1 = AIS interrupt is allowed.
AISI: Alarm Indication Signal Interrupt Status Register (R, Address = 15 Hex)
Symbol AISI[7:0] Position AISI.7-0 Default 00 H Description 0 = (Default), or after an AIS read operation 1 = Any transition on AISn. (Corresponding AISMn is set to 1.)
ADDP: Address Pointer Control Register (R/W, Address = 1F Hex)
Symbol Position Default 00 H Description Two kinds of configuration in this register can be set to switch between primary register bank and expanded register bank. When power up, the address pointer will point to the top address of primary register bank automatically. 00H = The address pointer points to the top address of primary register bank (default). AAH = The address pointer points to the top address of expanded register bank.
ADDP[7:0] ADDP.7-0
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Expanded Register Description e-SING: Single Rail Mode Setting Register (R/W, Expanded Address = 00 Hex)
Symbol SING[7:0] Position SING.7-0 Default 00 H Description 0 = Pin TDNn selects single rail mode or dual rail mode. (Default) 1 = Single rail mode enabled (with CRSn=0)
e-CODE: Encoder/Decoder Selection Register (R/W, Expanded Address = 01 Hex)
Symbol CODE[7:0] Position CODE.7-0 Default 00 H Description Line Code Selection. CODEn selects AMI or B8ZS/HDB3 encoder/decoder on per-channel basis with SINGn = 1 and CRSn = 0. 0 = B8ZS/HDB3 encoder/decoder enabled. (Default) 1 = AMI encoder/decoder enabled.
e-CRS: Clock Recovery Enable/Disable Selection Register (R/W, Expanded Address = 02 Hex)
Symbol CRS[7:0] Position CRS.7-0 Default 00 H Description 0 = Clock recovery enabled. (Default) 1 = Clock recovery disabled.
e-RPDN: Receiver n Powerdown Register (R/W, Expanded Address = 03 Hex)
Symbol RPDN[7:0] Position RPDN.7-0 Default 00 H 0 = Normal operation. (Default) 1 = Power down in receiver n. Description
e-TPDN: Transmitter n Powerdown Register (R/W, Expanded Address = 04 Hex)
Symbol TPDN[7:0] Position TPDN.7-0 Default 00 H Description 0 = Normal operation. (Default) 1 = Power down in Transmitter n (the corresponding transmit output driver enters a low power high impedance mode). Note that transmitter n is power down when either pin TCLKn is pulled to low or TPDNn is set to 1.
e-CZER: Consecutive Zero Detect Enable/Disable Register (R/W, Expanded Address = 05 Hex)
Symbol CZER[7:0] Position CZER.7-0 Default 00 H Description 0 = Excessive zero detect disabled. (Default) 1 = Excessive zero detect enabled for B8ZS/HDB3 decoder in single rail mode.
e-CODV: Code Violation Detect Enable/Disable Register (R/W, Expanded Address = 06 Hex)
Symbol CODV[7:0] Position CODV.7-0 Default 00 H Description 0 = Code Violation Detect enable for B8ZS/HDB3 decoder in single rail mode. (Default) 1 = Code Violation Detect disable.
e-EQUA: Receive Equalizer Enable/Disable Register (R/W, Expanded Address = 07 Hex)
Symbol EQUA[7:0] Position EQUA.7-0 Default 00 H Description 0 = Normal operation. (Default) 1 = Equalizer in Receiver n enabled, which can improved the receive performance when transmission length is more than 200 m.
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e-LBCF: Inband Loopback Configuration Register (R/W, Expanded Address = 08 Hex)
Symbol LBDE ALBE Position LBCF.7-6 LBCF.5 LBCF.4 Default 000 0 0 Description 0 = Normal Operation. (Default) 1 = Reserved. Loopback Detector Enable 0 = Inband loopback code detection is disabled. (Default) 1 = Inband loopback code detection is enabled. Automatic Loopback Enable. 0 = Automatic Inband Loopback disabled. 1 = Automatic Inband Loopback enabled. Loopback Activation Code Length. 00 = 5-bit long activation code in LBAC[7:3] is effective. 01 = 6-bit long activation code in LBAC[7:2] is effective. 10 = 7-bit long activation code in LBAC[7:1] is effective. 11 = 8-bit long activation code in LBAC[7:0] is effective. Loopback Deactivation Code Length. 00 = 5-bit long deactivation code in LBDC[7:3] is effective. 01 = 6-bit long deactivation code in LBDC[7:2] is effective. 10 = 7-bit long deactivation code in LBDC[7:1] is effective. 11 = 8-bit long deactivation code in LBDC[7:0] is effective. Note that all these bits in e-LBCF are global control.
LBAL[1:0]
LBCF.3-2
00
LBDL[1:0]
LBCF.1-0
00
e-LBAC: Inband Loopback Activation Code Register (R/W, Expanded Address = 09 Hex)
Symbol LBAC[7:0] Position LBAC.7-0 Default 00 H Description LBAC[7:0] = 8-bit (or 4-bit) repeating activate code is programmed with the length limitation in LBAL[1:0]. LBAC[7:1] = 7-bit repeating activate code is programmed with the length limitation in LBAL[1:0]. LBAC[7:2] = 6-bit (or 3-bit) repeating activate code is programmed with the length limitation in LBAL[1:0]. LBAC[7:3] = 5-bit repeating activate code is programmed with the length limitation in LBAL[1:0]. Note1: when setting a value in e-LBAC or e-LBDC that is less than 8-bits, the most significant bits must be replicated in the unused least significant bits. e.g. if setting a 5-bit code = 11000, the register value should be 11000110. Here b7 is repeated in b2; b6 is repeated in b1; b5 is repeated in bo. Note2: this register is global control.
e-LBDC: Inband Loopback Deactivation Code Register (R/W, Expanded Address = 0A Hex)
Symbol LBDC[7:0] Position LBDC.7-0 Default 00 H Description LBDC[7:0] = 8-bit (or 4-bit) repeating deactivate code is programmed with the length limitation in LBDL[1:0]. LBDC[7:1] = 7-bit repeating deactivate code is programmed with the length limitation in LBDL[1:0]. LBDC[7:2] = 6-bit (or 3-bit) repeating deactivate code is programmed with the length limitation in LBDL[1:0]. LBDC[7:3] = 5-bit repeating deactivate code is programmed with the length limitation in LBDL[1:0]. Note that this register is global control.
e-LBS: Inband Loopback Receive Status Register (R, Expanded Address = 0B Hex)
Symbol LBS[7:0] Position LBS.7-0 Default 00 H Description 0 = Normal operation (Default). Or loopback deactivation code detected . 1 = Loopback activation code detected.
e-LBM: Inband Loopback Interrupt Mask Register (R/W, Expanded Address = 0C Hex)
Symbol LBM[7:0] Position LBM.7-0 Default 00 H Description 0 = LBI interrupt is not allowed (Default) 1 = LBI interrupt is allowed.
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e-LBI: Inband Loopback Interrupt Status Register (R, Expanded Address = 0D Hex)
Symbol LBI[7:0] Position LBI.7-0 Default 00 H Description 0 = (Default). Or after a read of e-LBS operation. 1 = Any transition on e-LBSn. (Corresponding e-LBMn and bit LBDE in e-LBCF are both set to 1.)
e-LBGS: Inband Loopback Activation/Deactivation Code Generator Selection Register (R/W, Expanded Address = 0E Hex)
Symbol LBGS[7:0] Position LBGS.7-0 Default 00 H Description 0 = Activation Code Generator is selected in transmitter n. (Default) 1 = Deactivation Code Generator is selected in transmitter n.
e-LBGE: Inband Loopback Activation/Deactivation Code Generator Enable Register (R/W, Expanded Address = 0F Hex)
Symbol LBGE[7:0] Position LBGE.7-0 Default 00 H Description 0 = Activation/ Deactivation Code Generator for inband loopback is disabled in transmitter n. (Default) 1 = Activation/Deactivation Code Generator for inband loopback is enabled in transmitter n.
Reserved Registers: Primary Registers 16 - 1E and are reservered. Test Registers: Expand Registers 10 - 1E are test registers. They must be set to 0.
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IEEE STD 1149.1 JTAG TEST ACCESS PORT
The IDT82V2048 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction registers plus a Test Access Port (TAP) controller. Control of the TAP is achieved through signals applied to the Test Mode Select (TMS) and Test Clock (TCK) input pins. Data is shifted into the registers via the Test Data Input (TDI) pin, and shifted out of the registers via the Test Data Output (TDO) pin. Both TDI and TDO are clocked at a rate determined by TCK.
The JTAG boundary scan registers includes BSR (Boundary Scan Register), IDR (Device Identification Register), BR (Bypass Register) and IR (Instruction Register). These will be described in the following pages. Refer to Figure-21 for architecture. JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) The IR (Instruction Register) with instruction decode block is used to select the test to be executed or the data register to be accessed or both. The instructions are shifted in LSB first to this 3-bit register. See Table-17 for details of the codes and the instructions related.
Digital output pins
Digital input pins
parallel latched output
BSR (Boundary Scan Register)
IDR (Device Identification Register) TDI BR (Bypass Register)
MUX
MUX
IR (Instruction Register)
TDO
Control<6:0> TMS TRST TCK TAP (Test Access Port) Controller Select Tristate Enable
Figure - 21. JTAG Architecture
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TABLE - 17. INSTRUCTION REGISTER DESCRIPTION
IR CODE INSTRUCTION COMMENTS The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. The signal on the output pins can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. The normal path between IDT82V2048 logic and the I/O pins is maintained. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to bypass the device.
000
Extest
100
Sample / Preload
110 111
Idcode Bypass
TABLE - 18. DEVICE IDENTIFICATION REGISTER DESCRIPTION
BIT No. 0 1~11 12~27 28~31 COMMENTS Set to "1" Producer Number Part Number Device Revision
Bypass Register (BR) The BR consists of a single bit. It can provide a serial path between the TDI input and TDO output, bypassing the BSR to reduce test access times. Boundary Scan Register (BSR) The BSR can apply and read test patterns in parallel to or from all the digital I/O pins. The BSR is a 98 bits long shift register and is initialized and read using the instruction EXTEST or SAMPLE/ PRELOAD. Each pin is related to one or more bits in the BSR. Please refer to Table-19 for details of BSR bits and their functions. TEST ACCESS PORT CONTROLLER The TAP controller is a 16-state synchronous state machine. Figure22 shows its state diagram A description of each state follows. Note that the figure contains two main branches to access either the data or instruction registers. The value shown next to each state transition in this figure states the value present at TMS at each rising edge of TCK. Please refer to Table-20 for details of the state description.
JTAG DATA REGISTER Device Identification Register (IDR) The IDR can be set to define the producer number, part number and the device revision, which can be used to verify the proper version or revision number that has been used in the system under test. The IDR is 32 bits long and is partitioned as in Table-18. Data from the IDR is shifted out to TDO LSB first.
TABLE - 19. BOUNDARY SCAN REGISTER DESCRIPTION
BIT No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 BIT SYMBOL POUT0 PIN0 POUT1 PIN1 POUT2 PIN2 POUT3 PIN3 POUT4 PIN4 POUT5 PIN5 POUT6 PIN6 POUT7 PIN SIGNAL LP0 LP0 LP1 LP1 LP2 LP2 LP3 LP3 LP4 LP4 LP5 LP5 LP6 LP6 LP7 TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O COMMENTS
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TABLE - 19. BOUNDARY SCAN REGISTER DESCRIPTION (CONTINUED)
BIT No. 15 16 BIT SYMBOL PIN7 PIOS PIN SIGNAL LP7 N/A TYPE I/O COMMENTS Controls pin LP7~0. When "0", the pins are configured as outputs. The output values to the pins are set in POUT7~0. When "1", the pins are tristated. The input values to the pins are read in PIN7~0.
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
TCLK1 TDP1 TDN1 RCLK1 RDP1 RDN1 HZEN1 LOS1 TCLK0 TDP0 TDN0 RCLK0 RDP0 RDN0 HZEN0 LOS0 MODE1 LOS3 RDN3 RDP3 HZEN3 RCLK3 TDN3 TDP3 TCLK3 LOS2 RDN2 RDP2 HZEN2 RCLK2 TDN2 TDP2 TCLK2 INT ACK SDORDYS
TCLK1 TDP1 TDN1 RCLK1 RDP1 RDN1 N/A LOS1 TCLK0 TDP0 TDN0 RCLK0 RDP0 RDN0 N/A LOS0 MODE1 LOS3 RDN3 RDP3 N/A RCLK3 TDN3 TDP3 TCLK3 LOS2 RDN2 RDP2 N/A RCLK2 TDN2 TDP2 TCLK2 INT ACK N/A
I I I O O O O I I I O O O O I O O O O I I I O O O O I I I O O -
Controls pin RDP1, RDN1 and RCLK1. When "0", the outputs are enabled on the pins. When "1", the pins are tristated.
Controls pin RDP0, RDN0 and RCLK0. When "0", the outputs are enabled on the pins. When "1", the pins are tristated.
Controls pin RDP3, RDN3 and RCLK3. When "0", the outputs are enabled on the pins. When "1", the pins are tristated.
Controls pin RDP2, RDN2 and RCLK2. When "0", the outputs are enabled on the pins. When "1", the pins are tristated.
53 54 55
WRB RDB ALE
DS R/W ALE
Control pin ACK. When "0", the output is enabled on pin ACK . When "1", the pin is tristated.
I I I
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TABLE - 19. BOUNDARY SCAN REGISTER DESCRIPTION (CONTINUED)
BIT No. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 BIT SYMBOL CSB MODE0 TCLK5 TDP5 TDN5 RCLK5 RDP5 RDN5 HZEN5 LOS5 TCLK4 TDP4 TDN4 RCLK4 RDP4 RDN4 HZEN4 LOS4 OE CLKE LOS7 RDN7 RDP7 HZEN7 RCLK7 TDN7 TDP7 TCLK7 LOS6 RDN6 RDP6 HZEN6 RCLK6 TDN6 TDP6 TCLK6 MCLK MODE2 A4 A3 A2 A1 A0 PIN SIGNAL CS MODE0 TCLK5 TDP5 TDN5 RCLK5 RDP5 RDN5 N/A LOS5 TCLK4 TDP4 TDN4 RCLK4 RDP4 RDN4 N/A LOS4 OE CLKE LOS7 RDN7 RDP7 N/A RCLK7 TDN7 TDP7 TCLK7 LOS6 RDN6 RDP6 N/A RCLK6 TDN6 TDP6 TCLK6 MCLK MODE2 A4 A3 A2 A1 A0 TYPE I I I I I O O O O I I I O O O O I I O O O O I I I O O O O I I I I I I I I I I COMMENTS
Controls pin RDP5, RDN5 and RCLK5. When "0", the outputs are enabled on the pins. When "1", the pins are tristated.
Controls pin RDP4, RDN4 and RCLK4. When "0", the outputs are enabled on the pins. When "1", the pins are tristated.
Controls pin RDP7, RDN7 and RCLK7. When "0", the outputs are enabled on the pins. When "1", the pins are tristated.
Controls pin RDP6, RDN6 and RCLK6. When "0", the outputs are enabled on the pins. When "1", the pins are tristated.
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TABLE - 20. TAP CONTROLLER STATE DESCRIPTION
STATE Test Logic Reset DESCRIPTION In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register with the IDCODE instruction. Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is held high for at least 5 rising edges of TCK. The controller remains in this state while TMS is high. The device processor automatically enters this state at power-up. This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The instruction register and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller moves to the Select-DR state. This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR state and a scan sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller moves to the Select-IR-Scan state. In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction does not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low. In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward its serial output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-DR state. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into the parallel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes only in this state. All shift-register stages in the test data register selected by the current instruction retain their previous value and the instruction does not change during this state. This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction register is initiated. If TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction does not change during this state. In this controller state, the shift register contained in the instruction register loads a fixed value of `100' on the rising edge of TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or the Shift-IR state if TMS is held low. In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its serial output on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or remains in the Shift-IR state if TMS is held low.
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
Capture-IR
Shift-IR
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TABLE - 21. TAP CONTROLLER STATE DESCRIPTION (CONTINUED)
STATE Exit1-IR DESCRIPTION This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK. When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction retain their previous value.
Pause-IR
Exit2-IR
Update-IR
1
Test-logic Reset 0
0 Run Test/Idle
1
Select-DR 0 1 Capture-DR 0
1
Select-IR 0 1 Capture-IR 0
1
0 Shift-DR 1 Exit1-DR 0 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 1 Shift-IR 1 Exit1-IR 0
0
1
0
Figure - 22. JTAG State Diagram
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING
Symbol VDDA,VDDD VDDIO0,VDDIO1 VDDT0-7 Vin Parameter Core Power Supply I/O Power Supply Transmit Power Supply Input Voltage, Any Digital Pin Input Voltage, Any RTIP and RRING pin (1) Min -0.5 -0.5 -0.5 GND-0.5 GND-0.5 Max 4.0 4.0 7.0 5.5 VDDA+0.5 VDDD+0.5 Unit V V V V V
ESD Voltage, any pin (2) 2000 V Transient latch-up current, any pin 100 mA Input current, any digital pin (3) -10 10 mA Iin (3) 100 DC Input current, any analog pin mA Pd Maximum power dissipation in package 1.6 W C Tc Case Temperature 120 C Ts Storage Temperature -65 +150 CAUTION Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTE: 1. Referenced to ground 2. Human body model 3. Constant input current
RECOMMENDED OPERATING CONDITIONS
Symbol VDDA,VDDD VDDIO VDDT Parameter Core Power Supply I/O Power Supply Transmitter Supply 3.3V 5V Ambient operating temperature Output load at TTIP and TRING Average core power supply current (1) IO power supply current (4) Average transmitter power supply current, T1 mode (1, 2, 3) 50% ones density data: 100% ones density data: Min 3.13 3.13 3.13 4.75 -40 25 Typ 3.3 3.3 3.3 5.0 25 55 15 Max 3.47 3.47 3.47 5.25 85 65 25 230 440 Unit V V V V C mA mA mA
TA RL IVDD IVDDIO IVDDT
NOTE: 1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels. 2. Power consumption includes power absorbed by line load and external transmitter components. 3. T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length (LEN = 101). 4. Digital output is driving 50pF load, digital input is within 10% of the supply rails.
45
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
POWER CONSUMPTION
Symbol E1, 3.3V, 75 Load Parameter 50% ones density data: 100% ones density data: E1, 3.3V, 120 Load 50% ones density data: 100% ones density data: E1, 5.0V, 75 Load 50% ones density data: 100% ones density data: E1, 5.0V, 120 Load 50% ones density data: 100% ones density data: T1, 3.3V, 100 Load (3) 50% ones density data: 100% ones density data: T1, 5.0V, 100 Load (3) 50% ones density data: 100% ones density data: LEN 000 000 000 000 000 000 000 000 101 111 101 111 Min Typ 662 1100 576 930 910 1585 785 1315 820 1670 1185 2395 Max(1, 2) 1177 992 1690 1410 1792 2670 Unit mW mW mW mW mW mW
NOTE: 1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels. 2. Power consumption includes power absorbed by line load and external transmitter components. 3. T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length (LEN = 101).
DC CHARACTERISTICS
Symbol VIL Parameter Input Low Level Voltage MODE2, JAS, LPn pins VIM All other digital inputs pins Input Mid Level Voltage MODE2, JAS, LPn pins VIH Input High Voltage MODE2, JAS, LPn pins VOL VOH VMA IH IL II All other digital inputs pins Output Low level Voltage (1) (Iout=1.6mA) Output High level Voltage (1) (Iout=400A) Analog Input Quiescent Voltage (RTIP, RRING pin while floating) Input High Level Current (MODE2, JAS, LPn pin) Input Low Level Current (MODE2, JAS, LPn pin) Input Leakage Current TMS, TDI, TRST All other digital input pins Tri-state Leakage Current Output High Impedance on (TTIP, TRING Pins) 2 3 VDDIO+ 0.2 2.0 0.4 2.4 1.33 1.4 VDDIO 1.47 50 50 50 10 10 V V V V A A A A A K 1 VDDIO+0.2 3 1 2 VDDIO Min Typ Max 1 3 VDDIO-0.2 0.8 2 VDDIO-0.2 3 Unit
V
V
IZL Z OH
-10 -10 150
NOTE: 1. Output drivers will output CMOS logic levels into CMOS loads.
46
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TRANSMITTER CHARACTERISTICS
Symbol Parameter V0-p Output pulse amplitudes (1) E1, 75 load E1,120 load T1,100 load VO-S Zero (space) level E1, 75 load E1,120 load T1,100 load Transmit amplitude variation with supply Difference between pulse sequences for 17 consecutive pulses T PW Output Pulse Width at 50% of nominal amplitude E1: T1: Ratio of the amplitudes of Positive and Negative Pulses at the center of the pulse interval RTX Transmit Return Loss (2) 51 KHz - 102 KHz E1,75 102 KHz - 2.048 MHz 2.048 MHz - 3.072 MHz 51 KHz - 102 KHz E1,120 102 KHz - 2.048 MHz 2.048 MHz - 3.072 MHz 51 KHz - 102 KHz T1 102 KHz - 2.048 MHz (VDDT=5V) 2.048 MHz - 3.072 MHz JTXP-P Intrinsic Transmit Jitter (TCLK is jitter free, JA enable) E1: 20 HZ - 100 KHz T1: 10 Hz - 8 KHz 8 KHz - 40 KHz 10 Hz - 40 KHz wide band Td Transmit path delay (JA is disabled) Single rail Dual rail ISC Line short circuit current (3)
NOTE: 1. E1:measured at the line output ports; T1: measured at the DSX 2. Test at IDT82V2048 evaluation board 3. Measured at 2x9.5 series resistors and 1:2 transformer
Min 2.14 2.7 2.4 -0.237 -0.3 -0.15 -1
Typ 2.37 3.0 3.0
Max 2.6 3.3 3.6 0.237 0.3 0.15 +1 200
Unit V V V V V V % mV ns ns
232 338 0.95 15 15 15 15 15 15 15 15 15
244 350
256 362 1.05
dB dB dB dB dB dB dB dB dB 0.050 0.020 0.025 0.025 0.050 8 3 150 U.I. U.I.p-p U.I.p-p U.I.p-p U.I.p-p U.I. U.I. mA Ip-p
47
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
RECEIVER CHARACTERISTICS
Symbol ATT IA SIR SRE Parameter Permissible Cable Attenuation (E1:@1024kHz, T1:@772KHz) Input Amplitude Signal to Interference Ratio Margin (1) Data decision threshold (reference to peak input voltage) Data slicer threshold Analog loss of signal (2) Threshold: Hysteresis: Allowable consecutive zeros before LOS E1, G.775: E1, ETSI300233: T1, T1.231-1993 LOS reset Clock recovery mode Peak to Peak Intrinsic Receive Jitter (JA disabled) E1 (wide band): T1 (wide band): Jitter Tolerance E1: 1 Hz - 20 Hz 20 Hz - 2.4 KHz 18 KHz - 100 KHz T1: 0.1 Hz - 1 Hz 4.9 Hz - 300 Hz 10 KHz - 100 KHz Receiver Differential Input Impedance Receiver Common Mode Input Impedance to GND Receive Return Loss 51 KHz - 102 KHz 102 KHz - 2.048 MHz 2.048 MHz - 3.072 MHz Receive path delay Dual rail Single rail Min 0.1 -14 50 150 310 230 32 2048 175 12.5 0.0625 0.0625 18.0 1.5 0.2 138.0 28.0 0.4 120 10 20 20 20 3 8 % ones U.I. U.I. U.I. U.I. U.I. U.I. U.I. U.I. K K db dB dB U.I. U.I. Typ Max 15 0.8 Unit dB Vp dB % mV mV mV
JRX p-p JTRX
ZDM ZCM RRX
NOTE: 1. E1: per G.703, O.151 @6dB cable attenuation. T1: @655ft. of 22ABAM cable 2. The test circuit for this parameter is shown in Figure 12. The analog signal is measured on the Receiver line before the transformer (port A and port B in Figure 12). And the receive line is a T1/E1 cable simulator.
48
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
JITTER ATTENUATOR CHARACTERISTICS
Symbol Parameter f-3dB Jitter Transfer Function Corner (-3dB) Frequency Host mode E1, 32/64 bit FIFO JABW = 0: JABW = 1: T1, 32/64 bit FIFO JABW = 0: JABW = 1: Hardware mode E1 T1 Jitter Attenuator E1: (1) @ 3 Hz @ 40 Hz @ 400 Hz @ 100kHz T1: (2) @ 1 Hz @ 20 Hz @ 1kHz @ 1.4kHz @ 70kHz td Jitter Attenuator Latency Delay 32bit FIFO: 64bit FIFO: Input jitter tolerance before FIFO overflow or underflow 32bit FIFO: 64bit FIFO: Output jitter in remote loopback (3) Min Typ Max Unit
1.7 6.6 2.5 5 1.7 2.5
Hz Hz Hz Hz Hz Hz
-0.5 -0.5 +19.5 +19.5 0 0 +33.3 40 40 16 32 28 56 0.11
dB
dB
U.I. U.I. U.I. U.I. U.I.
NOTE: 1. Per G.736, see Fig-38. 2. Per AT&T pub.62411, see Fig-39. 3. Per ETSI CTR12/13 Output jitter.
49
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TRANSCEIVER TIMING CHARACTERISTICS
Symbol MCLK frequency E1: T1: MCLK tolerance MCLK duty cycle Transmit path TCLK frequency E1: T1: TCLK tolerance TCLK Duty Cycle Transmit Data Setup Time Transmit Data Hold Time Delay time of OE low to driver High Z Delay time of TCLK low to driver High Z Clock recovery capture range (1)
(2)
Parameter
Min
Typ 2.048 1.544
Max
Unit MHz
-100 40 2.048 1.544 -50 10 40 40 40 44 +/- 80 +/- 180 50 488 648 244 324 244 324 244 324 244 324 244 324
100 60
ppm %
MHz +50 90 1 48 ppm % ns ns us us ppm 60 519 689 285 389 285 389 % ns ns ns ns ns ns ns
t1 t2 Receive path
E1 T1 40 457 607 203 259 203 259 20 200 200 200 200 200 300
t4 t5 t6
t7 t8
t9
RCLK duty cycle RCLK pulse width (2) E1: T1: RCLK pulse width low time E1: T1: RCLK pulse width high time E1: T1: Rise/fall time (3) Receive Data Setup Time E1: T1: Receive Data Hold Time E1: T1: RDN/RDP pulse width (MCLK = H) (4) E1: T1:
NOTE: 1. Relative to nominal frequency, MCLK=+/-100 ppm 2. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823). 3. For all digital outputs. C load = 15 pF 4. Clock recovery is disabled in this mode.
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TCLK
t1
t2
TNn/TDPn TDNn/BPVIn
Figure - 24. Transmit System Interface Timing
t4 RCLK t6 t5
t7 RDPn/RDn (CLKE = 1) RDNn/CVn
t8
t7 RDPn/RDn (CLKE = 0) RDNn/CVn
t8
Figure - 25. Receive System Interface Timing
51
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
JTAG TIMING CHARACTERISTICS
Symbol Parameter t1 TCK Period t2 TMS to TCK setup Time TDI to TCK Setup Time t3 TCK to TMS Hold Time TCK to TDI Hold Time t4 TCK to TDO Delay Time Min 200 50 50 100 Typ Max Unit ns ns ns ns Comments
t1 TCK
t2 TMS TDI
t3
t4 TDO
Figure - 26. JTAG Interface Timing
52
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PARALLEL HOST INTERFACE TIMING CHARACTERISTICS
INTEL MODE READ TIMING CHARACTERISTICS
Parameter Min Typ Max 90 Active RD Pulse Width 0 Active CS to Active RD Setup Time 0 RD to Inactive CS Hold Time Inactive Valid Address to Inactive ALE Setup Time (in Multiplexed Mode) 5 0 Invalid RD to Address Hold Time (in Non-Multiplexed Mode) 7.5 15 Active RD to Data Output Enable Time 7.5 15 Inactive RD to Data Tri-State Delay Time 6 12 Active CS to RDY delay time 6 12 Inactive CS to RDY Tri-state Delay Time 20 Inactive RD to Inactive INT Delay Time Address Latch Enable Pulse Width (in Multiplexed Mode) 10 0 Address Latch Enable to RD Setup Time (in Multiplexed Mode) Address Setup time to Valid Data Time (in Non-Multiplexed Mode) 18 32 Inactive ALE to Valid Data Time (in Multiplexed Mode) t14 10 15 Inactive RD to Active RDY Delay Time t15 30 85 Active RD to Active RDY Delay Time t16 Inactive ALE to Address Hold Time (in Multiplexed Mode) 5 Note 1: the t1 is determined by the start time of the valid data when the RDY signal is not used. Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Unit Comments ns note 1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
53
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
t2
INDUSTRIAL TEMPERATURE RANGES
t3
CS RD ALE(=1)
t1
t13 A[7:0] t6 D[7:0] t8 RDY t15 INT DATA OUT t14 ADDRESS t7
t5
t9
t10
Figure - 27. Non-Multiplexed Intel Mode Read Timing
CS RD t11 ALE
t2
t3
t1 t12 t16 t4 t6 DATA OUT t14 t9 t7
t13
AD[7:0]
ADDRESS t8
RDY t15 INT t10
Figure - 28. Multiplexed Intel Mode Read Timing
54
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
INTEL MODE WRITE TIMING CHARACTERISTICS
Symbol Parameter t1 WR Pulse Width Active t2 Active CS to Active WR Setup Time t3 Inactive WR to Inactive CS Hold Time t4 Valid Address to Latch Enable Setup Time (in Multiplexed Mode) t5 Invalid WR to Address Hold Time (in Non-Multiplexed Mode) t6 Valid Data to Inactive WR Setup Time t7 Inactive WR to Data Hold Time t8 Active CS to Inactive RDY Delay Time t9 Active WR to Active RDY Delay Time t10 Inactive WR to Inactive RDY Delay Time t11 Invalid CS to RDY Tri-State Delay Time t12 Address Latch Enable Pulse Width (in Multiplexed Mode) t13 Inactive ALE to WR Setup Time (in Multiplexed Mode) t14 Inactive ALE to Address hold time (in Multiplexed Mode) t15 Address setup time to Inactive WR time (in Non-Multiplexed Mode) Note 1: the t1 can be 15ns when RDY signal is not used.
CS t2 WR ALE(=1) t15 A[7:0] ADDRESS t6 D[7:0] t8 RDY t9 t7 t5 t1 t3
Min 90 0 0 5 2 5 10 6 30 10 6 10 0 5 5
Typ Max Unit Comments ns note 1 ns ns ns ns ns ns 12 ns 85 ns 15 ns 12 ns ns ns ns ns
WRITE DATA t10 t11
Figure - 29. Non-Multiplexed Intel Mode Write Timing
t2 t3
CS WR t12 ALE t4 AD[7:0]
t1 t13
t14
t6
t7
ADDRESS t8 t9
WRITE DATA t11 t10
RDY
Figure - 30. Multiplexed Intel Mode Write Timing
55
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
MOTOROLA MODE READ TIMING CHARACTERISTICS
Parameter Min Typ Max Unit Comments 90 ns note 1 Active DS Pulse Width 0 ns Active CS to Active DS Setup Time 0 ns Inactive DS to Inactive CS Hold Time 0 ns Valid R/W to Active DS Setup Time 0.5 ns DS to R/W Hold Time Inactive ns Valid Address to Active DS Setup Time (in Non-Multiplexed Mode) 5 Valid Address to AS Setup Time (in Multiplexed Mode) t7 ns Active DS to Address Hold Time (in Non-Multiplexed Mode) 10 Active AS to Address Hold Time (in Multiplexed Mode) t8 ns Active DS to Data Valid Delay Time (in Non-Multiplexed Mode) 20 35 Active AS to Data Valid Delay Time ( in Multiplexed Mode) t9 7.5 15 ns Active DS to Data Output Enable Time t10 7.5 15 ns Inactive DS to Data Tri-State Delay Time t11 30 85 ns Active DS to Active ACK Delay Time t12 10 15 ns Inactive DS to Inactive ACK Delay Time t13 20 ns Inactive DS to Invalid INT Delay Time t14 5 ns AS to Active DS Setup Time (in Multiplexed Mode) Active Note 1: the t1 is determined by the start time of the valid data when the ACK signal is not used.
CS t4 R/W DS ALE(=1) A[7:0] D[7:0] t9 ACK INT
CS t2 R/W DS AS t6 AD[7:0] ACK t13 INT t7 ADDRESS t11 t4 t14 t8 t9 DATA OUT t12 t1 t5 t3
Symbol t1 t2 t3 t4 t5 t6
t5 t1 t3
t2
t6
t7 t8 DATA OUT t12 t11 t13 t10
ADDRESS
Figure - 31. Non-Multiplexed Motorola Mode Read Timing
t10
Figure - 32. Multiplexed Motorola Mode Read Timing
56
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
MOTOROLA MODE WRITE TIMING CHARACTERISTICS
Parameter Active DS Pulse Width Active CS to Active DS Setup Time Inactive DS to Inactive CS Hold Time Valid R/ W to Active DS Setup Time Inactive DS to R/W Hold Time Valid Address to Active DS Setup Time (in Non-Multiplexed Mode) Valid Address to AS Setup Time (in Multiplexed Mode) t7 Valid DS to Address Hold Time (in Non-Multiplexed Mode) Valid AS to Address Hold Time (in Multiplexed Mode) t8 Valid Data to Inactive DS Setup Time t9 Inactive DS to Data Hold Time t10 Active DS to Active ACK Delay Time t11 Inactive DS to Inactive ACK Delay Time t12 Active AS to Active DS (in Multiplexed Mode) t13 Inactive DS to Inactive AS Hold Time ( in Multiplexed Mode) Note 1: the t1 can be 15ns when the ACK signal is not used.
CS t4 R/W DS ALE(=1) A[7:0] D[7:0] t10 ACK t6 t2 t1 t3 t5
Symbol t1 t2 t3 t4 t5 t6
Min 90 0 0 10 0 10 10 5 10 30 10 0 15
Typ Max Unit Comments ns note 1 ns ns ns ns ns ns ns ns ns ns ns ns
85 15
t7 t8 t9 t11
ADDRESS WRITE DATA
Figure - 33. Non-Multiplexed Motorola Mode Write Timing
CS t2 R/W DS AS t6 AD[7:0] ACK t7 t10 t8 WRITE DATA t11 t9 t4 t12 t1 t5 t13 t3
ADDRESS
Figure - 34. Multiplexed Motorola Mode Writing Timing
57
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
SERIAL HOST INTERFACE TIMING CHARACTERISTICS
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Parameter SCLK High Time SCLK Low Time Active CS to SCLK Setup Time Last SCLK Hold Time to Inactive CS Time CS Idle Time SDI to SCLK Setup Time SCLK to SDI Hold Time Rise/Fall Time (any pin) SCLK Rise and Fall Time SCLK to SDO Valid Delay Time SCLK Falling Edge to SDO tri-state Hold Time (CLKE = 0) CS Rising Edge to SDO tri-state Hold Time (CLKE = 1) Min 25 25 10 50 50 5 5 Typ Max Unit Comments ns ns ns ns ns ns ns ns ns ns ns
100 50 100 100
CS t3 SCLK t6 SDI LSB CONTROL BYTE t7 LSB DATA BYTE t7 MSB t1 t2 t4 t5
Figure - 35. Serial Interface Write Timing
1 SCLK CS SDO 0 1 2 3 4 5 6 7 t4 t11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure - 36. Serial Interface Read Timing with CLKE = 0
1 SCLK CS SDO 0 1 2 3 4 5 6 t4 t11 7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure - 37. Serial Interface Read Timing with CLKE = 1
58
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
JITTER TOLERANCE PERFORMANCE
E1 JITTER TOLERANCE PERFORMANCE
1 10 3
100
18 UI @ 1.8 Hz
Jitter (UI)
G.823 IDT82V2048
10
1.5 UI @ 20 Hz
1
1.5 UI @ 2.4 kHz 0.2 UI @ 18 kHz
0.1 1 10 100 1 10
3
4 1 10
1 10
5
Frequency (Hz)
Figure - 38. E1 Jitter Tolerance Performance
Test condition: PRBS 2^15-1; Line code rule HDB3 is used.
T1 JITTER TOLERANCE PERFORMANCE
1 10 3
100
28 UI @ 4.9 Hz 28 UI @ 300 Hz
AT&T62411 IDT82V2048
Jitter (UI)
10
1
0.4 UI @ 10kHz
0.1 1 10 100
3 1 10
1 10
4
5 1 10
Frequency (Hz)
Figure - 39. T1 Jitter Tolerance Performance
Test condition: QRSS; Line code rule B8ZS is used.
59
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
JITTER TRANSFER PERFORMANCE
E1 JITTER TRANSFER PERFORMANCE
0.5 dB @ 3 Hz 0.5 dB @ 40 Hz
0
Gain (dB)
G.736
-20
-19.5 dB @ 400 Hz -19.5 dB @ 20 kHz f3dB = 6.5 Hz
IDT82V2048
-40
f3dB = 1.7 Hz
-60
1
10
100
1 103
1 104
1 105
Frequency (Hz)
Figure - 40. E1 Jitter Transfer Performance
Test condition: PRBS 2^15-1; Line code rule HDB3 is used.
T1 JITTER TRANSFER PERFORMANCE
0 dB @ 1 Hz
0
0.1 dB @ 40 Hz
0.5 dB @ 350 Hz
AT&T62411 GR-253-CORE TR-TSY-000009 IDT82V2048 Gain (dB)
-20
-6 dB @ 2 Hz
0 dB @ 20 Hz
f3dB = 2.5 Hz -33.3 dB @ 1 kHz -33.7 dB @ 2.5 kHz -40 dB @ 1.4 kHz -40 dB @ 70 kHz -49.2 dB @ 15 kHz
100 1 103 1 104 1 105
f3dB = 5 Hz
-40
-60 1
-60 dB @ 57 Hz
10
Frequency (Hz)
Figure - 41. T1 Jitter Transfer Performance
Test condition: QRSS; Line code rule B8ZS is used.
60
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXXXX Device Type XX X Process/ Temperature Range
Blank
Industrial (-40 C to +85 C)
BB DA
Plastic Ball Grid Array (PBGA, BB160) Thin Quad Flatpack (TQFP, DA144)
82V2048
T1/E1 Short Haul LIU
Data Sheet Document History
11/4/2001 11/20/2001 11/28/2001 11/29/2001 12/5/2001 12/24/2001 1/5/2002 1/24/2002 2/21/2002 3/25/2002 4/17/2002 5/7/2002 8/27/2002 1/15/2003 12/9/2003
pgs. 2, 3, 11, 19 pgs. 5, 6, 12, 14, 18, 19, 27, 30, 36, 44, 45, 46, 58 pgs. 5, 27, 30, 37 pgs. 5, 12 pgs. 9 pgs.44, 45 pgs. 23, 36 pgs. 2, 3, 10, 16, 45, 46 pgs. 15,19, 47 pgs. 1, 2, 60 pgs. 20 pgs. 15, 51, 52, 55 pgs. 23, 37 pgs. 1, 61 pgs. 23 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* for Tech Support: 408-330-1552 email: telecomhelp@idt.com
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc.
61

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